L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 10/27/2023
Public

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Document Table of Contents

1.1. Avalon-ST Interface with Optional SR-IOV for PCIe Introduction

Intel® Stratix® 10 FPGAs include a configurable, hardened protocol stack for PCI Express* that is compliant with PCI Express Base Specification 3.0. The Intel L-/H-Tile Avalon-ST for PCI Express IP Core supports Gen1, Gen2 and Gen3 data rates and x1, x2, x4, x8, or x16 configurations.

Figure 1.  Intel® Stratix® 10 PCIe Variant with Avalon-ST Interface
Table 1.   PCI Express* Data Throughput

The following table shows the theoretical link bandwidth of a PCI Express link for Gen1, Gen2, and Gen3 for 1, 2, 4, 8, and 16 lanes. This table provides bandwidths for a single transmit (TX) or receive (RX) channel. The numbers double for duplex operation. The protocol specifies 2.5 giga-transfers per second (GT/s) for Gen1, 5.0 GT/s for Gen2, and 8.0 GT/s for Gen3. Gen1 and Gen2 use 8B/10B encoding which introduces a 20% overhead. Gen3 uses 128b/130b encoding which introduces about 1.6% overhead.

Link Width
×1 ×2 ×4 ×8 ×16

PCI Express Gen1 (2.5 Gbps)

2

4

8

16

32

PCI Express Gen2 (5.0 Gbps)

4

8

16

32

64

PCI Express Gen3 (8.0 Gbps)

7.87

15.75

31.5

63

126