L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 10/27/2023
Public

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Document Table of Contents

4.6.4. Slot Capabilities

Table 21.  Slot Capabilities  

Parameter

Value

Description

Use Slot register

On/Off

This parameter is only supported in Root Port mode. The slot capability is required for Root Ports if a slot is implemented on the port. Slot status is recorded in the PCI Express Capabilities register.

Defines the characteristics of the slot. You turn on this option by selecting Enable slot capability. Refer to the figure below for bit definitions.

Slot power scale

0–3

Specifies the scale used for the Slot power limit. The following coefficients are defined:

  • 0 = 1.0x
  • 1 = 0.1x
  • 2 = 0.01x
  • 3 = 0.001x

The default value prior to hardware and firmware initialization is b’00. Writes to this register also cause the port to send the Set_Slot_Power_Limit Message.

Refer to Section 6.9 of the PCI Express Base Specification Revision for more information.

Slot power limit

0–255

In combination with the Slot power scale value, specifies the upper limit in watts on power supplied by the slot. Refer to Section 7.8.9 of the PCI Express Base Specification for more information.

Slot number

0-8191

Specifies the slot number.

Figure 20. Slot Capability