L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 10/27/2023
Public

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Document Table of Contents

6.1. Interfaces

This section describes the top-level interfaces in the Intel L-/H-Tile Avalon-ST for PCI Express IP core.
The colors and variables in the figure below specify the following information:
  • Orange text: signal is only available for L-Tile devices
  • Deep red/brown text: signal is only available for H-Tile devices
  • Blue text: PIPE interface signals, only available for simulation
  • <w>: the width of the Avalon® -ST data interface
  • <n>: 2 for the 512-bit interface and 1 for the 256-bit interface
  • <r>: 6 for the 512-bit interface and 3 for the 256-bit
Figure 33.  Intel L-/H-Tile Avalon-ST for PCI Express IP Top-Level Signals