L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 10/27/2023
Public

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Document Table of Contents

4.6.3. MSI and MSI-X Capabilities

Table 20.  MSI and MSI-X Capabilities 

Parameter

Value

Address

Description

MSI messages requested

1, 2, 4, 8, 16, 32

0x050[31:16]

Specifies the number of messages the Application Layer can request. Sets the value of the Multiple Message Capable field of the Message Control register.

Only PFs support MSI. When you enabled SR-IOV, PFs must use MSI-X.

MSI-X Capabilities

Implement MSI-X

On/Off

 

When On, adds the MSI-X capability structure, with the parameters shown below.

When you enable SR-IOV, you must enable MSI-X.

Bit Range  

Table size

[10:0]

0x068[26:16]

System software reads this field to determine the MSI-X Table size <n>, which is encoded as <n–1>. For example, a returned value of 2047 indicates a table size of 2048. This field is read-only in the MSI-X Capability Structure. Legal range is 0–2047 (211).

VF’s share a common Table Size. VF Table BIR/Offset, and PBA BIR/Offset are fixed at compile time. BAR4 accesses these tables.

The table Offset field = 0x600. The PBA Offset field =0x400 for SRIOV. You must implement an MSI-X table. If you do not intend to use MSI-X, you may program the table size to 1.

Table offset

[31:3]

 

Points to the base of the MSI-X Table. The entire Table address is comprised of the Table Offset, which provides the upper 29 bits, and the Table BAR Indicator, which provides the lower three bits.

When read by software, the lower three bits are set to zero to create quad-word alignment. This field is read-only.

Table BAR indicator

[2:0]

 
Specifies which one of a function’s BARs, located beginning at 0x10 in Configuration Space, is used to map the MSI-X table into memory space. This field is read-only. Legal range is 0–5 as shown in the following encodings:
  • 3'b000: BAR0
  • 3'b001: BAR1
  • 3'b010: BAR2
  • 3'b011: BAR3
  • 3'b100: BAR4
  • 3'b101: BAR5

Pending bit array (PBA) offset

[31:3]

 

Points to the base of the MSI-X PBA. The entire PBA address is comprised of the PBA Offset, which provides the upper 29 bits, and the Pending BAR Indicator, which provides the lower three bits.

When read by software, the lower three bits are set to zero to create quad-word alignment. This field is read-only in the MSI-X Capability Structure. 2

Pending BAR indicator

[2:0]

 
Specifies the function Base Address registers, located beginning at 0x10 in Configuration Space, that maps the MSI-X PBA into memory space. This field is read-only in the MSI-X Capability Structure. Legal range is 0–5 as shown in the following encodings:
  • 3'b000: BAR0
  • 3'b001: BAR1
  • 3'b010: BAR2
  • 3'b011: BAR3
  • 3'b100: BAR4
  • 3'b101: BAR5
2 Throughout this user guide, the terms word, DWORD and qword have the same meaning that they have in the PCI Express Base Specification. A word is 16 bits, a DWORD is 32 bits, and a qword is 64 bits.