L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 10/27/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

8.1.10.5. Page Size Registers

Table 76.  Supported Page Size Register - 0x1D4

Bits

Register Description

Default Value

Access

[31:0]

Supported Page Sizes. Specifies the page sizes supported by the device

Set in Platform Designer

RO

Table 77.  System Page Size Register - 0x1D8

Bits

Register Description

Default Value

Access

[31:0]

Supported Page Sizes. Specifies the page size currently in use.

Set in Platform Designer

RO