L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 10/27/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.1.2. Avalon-ST 256-Bit RX Interface

The Application Layer receives data from the Transaction Layer of the PCIe IP core over the Avalon-ST RX interface. This is a 256-bit interface.
Table 31.  256‑Bit Avalon-ST RX Datapath

Signal

Direction

Description

rx_st_data[255:0]

Output

Receive data bus. The Application Layer receives data from the Transaction Layer on this bus. The data on this bus is valid when rx_st_valid is asserted.

Refer to the TLP Header and Data Alignment for the Avalon-ST TX and Avalon-ST RX Interfaces for the layout of TLP headers and data.

rx_st_sop

Output

Marks the first cycle of the TLP when both rx_st_sop and rx_st_valid are asserted.

rx_st_eop

Output

Marks the last cycle of the TLP when both rx_st_eop and rx_st_valid are asserted.

rx_st_ready

Input

Indicates that the Application Layer is ready to accept data. The Application Layer deasserts this signal to throttle the data stream.

rx_st_valid

Output

Qualifies rx_st_data into the Application Layer.

The rx_st_ready to rx_st_valid latency for Stratix® 10 devices is 17 cycles. When rx_st_ready deasserts, rx_st_valid will deassert within 17 cycles. When rx_st_ready reasserts, rx_st_valid will reassert within 17 cycles if there is more data to send. To achieve the best throughput, Intel recommends that you size the RX buffer to avoid the deassertion of rx_st_ready. Refer to Avalon-ST RX Interface rx_st_valid Deasserts for a timing diagram that illustrates this behavior.

rx_st_bar_range[2:0]

Output

Specifies the bar for the TLP being output. The following encodings are defined:
  • 000: Memory Bar 0
  • 001: Memory Bar 1
  • 010: Memory Bar 2
  • 011: Memory Bar 3
  • 100: Memory Bar 4
  • 101: Memory Bar 5
  • 110: I/O BAR
  • 111: Expansion ROM BAR

The data on this bus is valid when rx_st_sop and rx_st_valid are both asserted.

rx_st_vf_active H-Tile Output

When asserted, the received TLP targets a VF bar. Valid if rx_st_sop and rx_st_valid are asserted. When deasserted, the TLP targets a PF and the rx_st_func_num port drives the function number.

Valid when multiple virtual functions are enabled.

rx_st_func_num[1:0] H-Tile

Output

Specifies the target physical function number of the received TLP. The application uses this information to route packets for both request and completion TLPs. For completion TLPs, specifies the PF number of the requestor for this completion TLP. If the TLP targets a VF[<m>, <n>], this bus carries the PF<m> information.

Valid when multiple physical functions are enabled.

These outputs are qualified by rx_st_sop and rx_st_valid.

     

rx_st_vf_num[log2 <x>-1:0] H-Tile

Output

Specifies the target VF number rx_st_data[255:0] of the received TLP. The application uses this information for both request and completion TLPs. For completion TLPs, specifies the VF number of the requester for this completion TLP. <x> is the number of VFs.

Valid when rx_st_vf_active is asserted. If the TLP targeting at VF[<m>, <n>] this bus carries the VF<n> information.

Valid when multiple virtual functions are enabled.

These outputs are qualified by rx_st_sop and rx_st_valid.

rx_st_empty[2:0]   Specifies the number of dwords that are empty, valid during cycles when the rx_st_eop signal is asserted. Not interpreted when rx_st_eop is deasserted.