L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 10/27/2023
Public

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6.1.22. PLL IP Reconfiguration

The PLL reconfiguration interface is an Avalon® -MM slave interface with an 11‑bit address and a 32‑bit data bus. Use this bus to dynamically modify the value of PLL registers that are read-only at run time.

To ensure proper system operation, reset or repeat device enumeration of the PCIe* link after changing the value of read-only PLL registers.

These signals are present when you turn on Enable Transceiver dynamic reconfiguration on the Configuration, Debug and Extension Options tab using the parameter editor.

Table 50.  Hard IP Reconfiguration Signals The same set of signals are available for PLL1.

Signal

Direction

Description

xcvr_reconfig_clk

Input

Reconfiguration clock. The frequency range for this clock is 100–125 MHz.

xcvr_reconfig_rst_n

Input

Active-low Avalon® -MM reset for this interface.

xcvr_reconfig_address[14:0]

Input

The 11‑bit reconfiguration address.

xcvr_reconfig_read

Input

Read signal. This interface is not pipelined. You must wait for the return of the xcvr_reconfig_readdata[31:0] from the current read before starting another read operation.

xcvr_reconfig_readdata[31:0]

Output

32‑bit read data. xcvr_reconfig_readdata[31:0] is valid on the third cycle after the assertion of xcvr_reconfig_read.

xcvr_reconfig_write

Input

Write signal.

xcvr_reconfig_writedata[31:0]

Input

32‑bit write data.

xcvr_reconfig_waitrequest Output When asserted, indicates that the IP core is not ready to respond to a request.