L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

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ID 683111
Date 10/27/2023
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Quick Start Guide 3. Interface Overview 4. Parameters 5. Designing with the IP Core 6. Block Descriptions 7. Interrupts 8. Registers 9. Testbench and Design Example 10. Troubleshooting and Observing the Link A. PCI Express Core Architecture B. TX Credit Adjustment Sample Code C. Root Port Enumeration D. Document Revision History
1. Introduction x
1.1. Avalon-ST Interface with Optional SR-IOV for PCIe Introduction 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Recommended Fabric Speed Grades 1.6. Performance and Resource Utilization 1.7. Transceiver Tiles 1.8. PCI Express IP Core Package Layout 1.9. Channel Availability
2. Quick Start Guide x
2.1. Design Components 2.2. Hardware and Software Requirements 2.3. Directory Structure 2.4. Generating the Design Example 2.5. Simulating the Design Example 2.6. Compiling the Design Example and Programming the Device 2.7. Installing the Linux Kernel Driver 2.8. Running the Design Example Application
3. Interface Overview x
3.1. Avalon-ST RX Interface 3.2. Avalon-ST TX Interface 3.3. TX Credit Interface 3.4. TX and RX Serial Data 3.5. Clocks 3.6. Function-Level Reset (FLR) Interface 3.7. Control Shadow Interface for SR-IOV 3.8. Configuration Extension Bus Interface 3.9. Hard IP Reconfiguration Interface 3.10. Interrupt Interfaces 3.11. Power Management Interface 3.12. Reset 3.13. Transaction Layer Configuration Interface 3.14. PLL Reconfiguration Interface 3.15. PIPE Interface (Simulation Only)
4. Parameters x
4.1. Stratix 10 Avalon-ST Settings 4.2. Multifunction and SR-IOV System Settings 4.3. Base Address Registers 4.4. Device Identification Registers 4.5. TPH/ATS Capabilities 4.6. PCI Express and PCI Capabilities Parameters 4.7. Configuration, Debug and Extension Options 4.8. PHY Characteristics 4.9. Example Designs
4.6. PCI Express and PCI Capabilities Parameters x
4.6.1. Device Capabilities 4.6.2. Link Capabilities 4.6.3. MSI and MSI-X Capabilities 4.6.4. Slot Capabilities 4.6.5. Power Management 4.6.6. Vendor Specific Extended Capability (VSEC)
5. Designing with the IP Core x
5.1. Generation 5.2. Simulation 5.3. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 5.4. Integration and Implementation 5.5. Required Supporting IP Cores 5.6. Channel Layout and PLL Usage
5.2. Simulation x
5.2.1. Selecting Serial or PIPE Simulation
5.4. Integration and Implementation x
5.4.1. Clock Requirements 5.4.2. Reset Requirements
5.5. Required Supporting IP Cores x
5.5.1. Hard Reset Controller 5.5.2. TX PLL
6. Block Descriptions x
6.1. Interfaces 6.2. Errors reported by the Application Layer 6.3. Power Management 6.4. Transaction Ordering 6.5. RX Buffer
6.1. Interfaces x
6.1.1. TLP Header and Data Alignment for the Avalon-ST RX and TX Interfaces 6.1.2. Avalon-ST 256-Bit RX Interface 6.1.3. Avalon-ST 512-Bit RX Interface 6.1.4. Avalon-ST 256-Bit TX Interface 6.1.5. Avalon-ST 512-Bit TX Interface 6.1.6. TX Credit Interface 6.1.7. Interpreting the TX Credit Interface 6.1.8. Clocks 6.1.9. Update Flow Control Timer and Credit Release 6.1.10. Function-Level Reset (FLR) Interface 6.1.11. Resets 6.1.12. Interrupts 6.1.13. Control Shadow Interface for SR-IOV 6.1.14. Transaction Layer Configuration Space Interface 6.1.15. Configuration Extension Bus Interface 6.1.16. Hard IP Status Interface 6.1.17. Hard IP Reconfiguration 6.1.18. Power Management Interface 6.1.19. Serial Data Interface 6.1.20. PIPE Interface 6.1.21. Test Interface 6.1.22. PLL IP Reconfiguration 6.1.23. Message Handling
6.1.2. Avalon-ST 256-Bit RX Interface x
6.1.2.1. Avalon-ST RX Interface Three- and Four-Dword TLPs 6.1.2.2. Avalon-ST RX Interface rx_st_ready Deasserts for the 256-Bit Interface 6.1.2.3. Avalon-ST RX Interface rx_st_valid Deasserts 6.1.2.4. Avalon-ST RX Back-to-Back Transmission 6.1.2.5. Avalon-ST RX Interface Single-Cycle TLPs
6.1.3. Avalon-ST 512-Bit RX Interface x
6.1.3.1. PCIe TLP Layout Using the 512-Bit Interface
6.1.4. Avalon-ST 256-Bit TX Interface x
6.1.4.1. Avalon-ST TX Three- and Four-Dword TLPs 6.1.4.2. Avalon-ST TX Interface tx_st_ready Deassertion 6.1.4.3. Assertion and Deassertion of Avalon-ST TX Interface tx_st_valid
6.1.12. Interrupts x
6.1.12.1. MSI and Legacy Interrupts
6.1.23. Message Handling x
6.1.23.1. Endpoint Received Messages 6.1.23.2. Endpoint Transmitted Messages
6.2. Errors reported by the Application Layer x
6.2.1. Error Handling
6.3. Power Management x
6.3.1. Endpoint D3 Entry 6.3.2. End Point D3 Exit 6.3.3. Exit from D3 hot 6.3.4. Exit from D3 cold 6.3.5. Active State Power Management
6.4. Transaction Ordering x
6.4.1. TX TLP Ordering 6.4.2. RX TLP Ordering
6.5. RX Buffer x
6.5.1. Retry Buffer 6.5.2. Configuration Retry Status
7. Interrupts x
7.1. Interrupts for Endpoints
7.1. Interrupts for Endpoints x
7.1.1. MSI and Legacy Interrupts 7.1.2. MSI-X 7.1.3. Implementing MSI-X Interrupts 7.1.4. Legacy Interrupts
8. Registers x
8.1. Configuration Space Registers
8.1. Configuration Space Registers x
8.1.1. Register Access Definitions 8.1.2. PCI Configuration Header Registers 8.1.3. PCI Express Capability Structures 8.1.4. Intel Defined VSEC Capability Header 8.1.5. General Purpose Control and Status Register 8.1.6. Uncorrectable Internal Error Status Register 8.1.7. Uncorrectable Internal Error Mask Register 8.1.8. Correctable Internal Error Status Register 8.1.9. Correctable Internal Error Mask Register 8.1.10. SR-IOV Virtualization Extended Capabilities Registers Address Map
8.1.4. Intel Defined VSEC Capability Header x
8.1.4.1. Intel Defined Vendor Specific Header 8.1.4.2. Intel Marker 8.1.4.3. JTAG Silicon ID 8.1.4.4. User Configurable Device and Board ID
8.1.10. SR-IOV Virtualization Extended Capabilities Registers Address Map x
8.1.10.1. ARI Enhanced Capability Header 8.1.10.2. SR-IOV Enhanced Capability Registers 8.1.10.3. Initial VFs and Total VFs Registers 8.1.10.4. VF Device ID Register 8.1.10.5. Page Size Registers 8.1.10.6. VF Base Address Registers (BARs) 0-5 8.1.10.7. Secondary PCI Express Extended Capability Header 8.1.10.8. Lane Status Registers 8.1.10.9. Transaction Processing Hints (TPH) Requester Enhanced Capability Header 8.1.10.10. TPH Requester Capability Register 8.1.10.11. TPH Requester Control Register 8.1.10.12. Address Translation Services ATS Enhanced Capability Header 8.1.10.13. ATS Capability Register and ATS Control Register
9. Testbench and Design Example x
9.1. Endpoint Testbench 9.2. Test Driver Module 9.3. Root Port BFM Overview 9.4. BFM Procedures and Functions
9.1. Endpoint Testbench x
9.1.1. Endpoint Testbench for SR-IOV
9.3. Root Port BFM Overview x
9.3.1. BFM Memory Map 9.3.2. Configuration Space Bus and Device Numbering 9.3.3. Configuration of Root Port and Endpoint 9.3.4. Issuing Read and Write Transactions to the Application Layer
9.4. BFM Procedures and Functions x
9.4.1. ebfm_barwr Procedure 9.4.2. ebfm_barwr_imm Procedure 9.4.3. ebfm_barrd_wait Procedure 9.4.4. ebfm_barrd_nowt Procedure 9.4.5. ebfm_cfgwr_imm_wait Procedure 9.4.6. ebfm_cfgwr_imm_nowt Procedure 9.4.7. ebfm_cfgrd_wait Procedure 9.4.8. ebfm_cfgrd_nowt Procedure 9.4.9. BFM Configuration Procedures 9.4.10. BFM Shared Memory Access Procedures 9.4.11. BFM Log and Message Procedures 9.4.12. Verilog HDL Formatting Functions
9.4.9. BFM Configuration Procedures x
9.4.9.1. ebfm_cfg_rp_ep Procedure 9.4.9.2. ebfm_cfg_decode_bar Procedure
9.4.10. BFM Shared Memory Access Procedures x
9.4.10.1. Shared Memory Constants 9.4.10.2. shmem_write Task 9.4.10.3. shmem_read Function 9.4.10.4. shmem_display Verilog HDL Function 9.4.10.5. shmem_fill Procedure 9.4.10.6. shmem_chk_ok Function
9.4.11. BFM Log and Message Procedures x
9.4.11.1. ebfm_display Verilog HDL Function 9.4.11.2. ebfm_log_stop_sim Verilog HDL Function 9.4.11.3. ebfm_log_set_suppressed_msg_mask Task 9.4.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 9.4.11.5. ebfm_log_open Verilog HDL Function 9.4.11.6. ebfm_log_close Verilog HDL Function
9.4.12. Verilog HDL Formatting Functions x
9.4.12.1. himage1 9.4.12.2. himage2 9.4.12.3. himage4 9.4.12.4. himage8 9.4.12.5. himage16 9.4.12.6. dimage1 9.4.12.7. dimage2 9.4.12.8. dimage3 9.4.12.9. dimage4 9.4.12.10. dimage5 9.4.12.11. dimage6 9.4.12.12. dimage7
10. Troubleshooting and Observing the Link x
10.1. Troubleshooting 10.2. PCIe Link Inspector Overview
10.1. Troubleshooting x
10.1.1. Simulation Fails To Progress Beyond Polling.Active State 10.1.2. Hardware Bring-Up Issues 10.1.3. Link Training 10.1.4. Link Hangs in L0 State 10.1.5. Use Third-Party PCIe Analyzer
10.2. PCIe Link Inspector Overview x
10.2.1. PCIe* Link Inspector Hardware
10.2.1. PCIe* Link Inspector Hardware x
10.2.1.1. Enabling the PCIe* Link Inspector 10.2.1.2. Launching the PCIe* Link Inspector 10.2.1.3. The PCIe* Link Inspector LTSSM Monitor 10.2.1.4. Accessing the Configuration Space and Transceiver Registers 10.2.1.5. Additional Status Commands
10.2.1.3. The PCIe* Link Inspector LTSSM Monitor x
10.2.1.3.1. LTSSM Monitor Registers 10.2.1.3.2. ltssm_save2file <file_name> 10.2.1.3.3. ltssm_file2console 10.2.1.3.4. ltssm_debug_check 10.2.1.3.5. ltssm_display <num_states> 10.2.1.3.6. ltssm_save_oldstates
10.2.1.4. Accessing the Configuration Space and Transceiver Registers x
10.2.1.4.1. PCIe* Link Inspector Commands 10.2.1.4.2. NPDME PLL and Channel Commands 10.2.1.4.3. Register Address Map
10.2.1.5. Additional Status Commands x
10.2.1.5.1. Displaying PLL Lock and Calibration Status Registers
A. PCI Express Core Architecture x
A.1. Transaction Layer A.2. Data Link Layer A.3. Physical Layer
D. Document Revision History x
D.1. Document Revision History for the Intel® L- and H-Tile Avalon® Streaming and Single-Root I/O Virtualization (SR-IOV) IP for PCI Express* User Guide
1. Introduction
2. Quick Start Guide
3. Interface Overview
4. Parameters
5. Designing with the IP Core
6. Block Descriptions
7. Interrupts
8. Registers
9. Testbench and Design Example
10. Troubleshooting and Observing the Link
A. PCI Express Core Architecture
B. TX Credit Adjustment Sample Code
C. Root Port Enumeration
D. Document Revision History

6.1.20. PIPE Interface

The Intel® Stratix® 10 PIPE interface compiles with the PHY Interface for the PCI Express Architecture PCI Express 3.0 specification.
Table 49.  PIPE Interface

Signal

Direction

Description

txdata[31:0] Output

Transmit data.

txdatak[3:0] Output Transmit data control character indication.
txcompl Output Transmit compliance. This signal drives the TX compliance pattern. It forces the running disparity to negative in Compliance Mode (negative COM character).
txelecidle Output Transmit electrical idle. This signal forces the tx_out<n> outputs to electrical idle.
txdetectrx Output Transmit detect receive. This signal tells the PHY layer to start a receive detection operation or to begin loopback.
powerdown[1:0] Output Power down. This signal requests the PHY to change the power state to the specified state (P0, P0s, P1, or P2).
txmargin[2:0] Output Transmit VOD margin selection. The value for this signal is based on the value from the Link Control 2 Register.
txdeemp Output Transmit de-emphasis selection. The Intel L-/H-Tile Avalon-ST for PCI Express IP sets the value for this signal based on the indication received from the other end of the link during the Training Sequences (TS). You do not need to change this value.
txswing Output When asserted, indicates full swing for the transmitter voltage. When deasserted indicates half swing.
txsynchd[1:0] Output

For Gen3 operation, specifies the receive block type. The following encodings are defined:

  • 2'b01: Ordered Set Block
  • 2'b10: Data Block
Designs that do not support Gen3 can ground this signal.
txblkst[3:0] Output For Gen3 operation, indicates the start of a block in the transmit direction. pipe spec
txdataskip Output

For Gen3 operation. Allows the MAC to instruct the TX interface to ignore the TX data interface for one clock cycle. The following encodings are defined:

  • 1’b0: TX data is invalid
  • 1’b1: TX data is valid
rate[1:0] Output

The 2‑bit encodings have the following meanings:

  • 2’b00: Gen1 rate (2.5 Gbps)
  • 2’b01: Gen2 rate (5.0 Gbps)
  • 2’b1X: Gen3 rate (8.0 Gbps)
rxpolarity Output

Receive polarity. This signal instructs the PHY layer to invert the polarity of the 8B/10B receiver decoding block.

currentrxpreset[2:0] Output For Gen3 designs, specifies the current preset.
currentcoeff[17:0] Output

For Gen3, specifies the coefficients to be used by the transmitter. The 18 bits specify the following coefficients:

  • [5:0]: C-1
  • [11:6]: C0
  • [17:12]: C+1

rxeqeval

Output For Gen3, the PHY asserts this signal when it begins evaluation of the transmitter equalization settings. The PHY asserts Phystatus when it completes the evaluation. The PHY deasserts rxeqeval to abort evaluation.

rxeqinprogress

Output For Gen3, the PHY asserts this signal when it begins link training. The PHY latches the initial coefficients from the link partner.

invalidreq

Output For Gen3, indicates that the Link Evaluation feedback requested a TX equalization setting that is out-of-range. The PHY asserts this signal continually until the next time it asserts rxeqeval.
rxdata[31:0] Input Receive data control. Bit 0 corresponds to the lowest-order byte of rxdata, and so on. A value of 0 indicates a data byte. A value of 1 indicates a control byte. For Gen1 and Gen2 only.
rxdatak[3:0] Input Receive data control. This bus receives data on lane. Bit 0 corresponds to the lowest-order byte of rxdata, and so on. A value of 0 indicates a data byte. A value of 1 indicates a control byte. For Gen1 and Gen2 only.
phystatus Input PHY status. This signal communicates completion of several PHY requests. pipe spec
rxvalid Input Receive valid. This signal indicates symbol lock and valid data on rxdata and rxdatak.
rxstatus[2:0] Input Receive status. This signal encodes receive status, including error codes for the receive data stream and receiver detection.
rxelecidle Input Receive electrical idle. When asserted, indicates detection of an electrical idle. pipe spec
rxsynchd[3:0] Input

For Gen3 operation, specifies the receive block type. The following encodings are defined:

  • 2'b01: Ordered Set Block
  • 2'b10: Data Block
Designs that do not support Gen3 can ground this signal.
rxblkst[3:0] Input For Gen3 operation, indicates the start of a block in the receive direction.
rxdataskip Input

For Gen3 operation. Allows the PCS to instruct the RX interface to ignore the RX data interface for one clock cycle. The following encodings are defined:

  • 1’b0: RX data is invalid
  • 1’b1: RX data is valid

dirfeedback[5:0]

Input For Gen3, provides a Figure of Merit for link evaluation for H tile transceivers. The feedback applies to the following coefficients:
  • dirfeedback[5:4]: Feedback applies to C+1
  • dirfeedback[3:2]: Feedback applies to C0
  • dirfeedback[1:0]: Feedback applies to C-1

The following feedback encodings are defined:

  • 2'b00: No change
  • 2'b01: Increment
  • 2'b10: Decrement
  • 2/b11: Reserved
simu_mode_pipe Input When set to 1, the PIPE interface is in simulation mode.
sim_pipe_pclk_in Input

This clock is used for PIPE simulation only, and is derived from the refclk. It is the PIPE interface clock used for PIPE mode simulation.

sim_pipe_rate[1:0] Output

The 2-bit encodings have the following meanings:

  • 2’b00: Gen1 rate (2.5 Gbps)
  • 2’b01: Gen2 rate (5.0 Gbps)
  • 2’b10: Gen3 rate (8.0 Gbps)
sim_ltssmstate[5:0] Output

LTSSM state: The following encodings are defined:

  • 6'h00 - Detect.Quiet
  • 6'h01 - Detect.Active
  • 6'h02 - Polling.Active
  • 6'h03 - Polling.Compliance
  • 6'h04 - Polling.Configuration
  • 6'h05 - PreDetect.Quiet
  • 6'h06 - Detect.Wait
  • 6'h07 - Configuration.Linkwidth.Start
  • 6'h08 - Configuration.Linkwidth.Accept
  • 6'h09 - Configuration.Lanenum.Wait
  • 6'h0A - Configuration.Lanenum.Accept
  • 6'h0B - Configuration.Complete
  • 6'h0C - Configuration.Idle
  • 6'h0D - Recovery.RcvrLock
  • 6'h0E - Recovery.Speed
  • 6'h0F - Recovery.RcvrCfg
  • 6'h10 - Recovery.Idle
  • 6'h20 - Recovery.Equalization Phase 0
  • 6'h21 - Recovery.Equalization Phase 1
  • 6'h22 - Recovery.Equalization Phase 2
  • 6'h23 - Recovery.Equalization Phase 3
  • 6'h11 - L0
  • 6'h12 - L0s
  • 6'h13 - L123.SendEIdle
  • 6'h14 - L1.Idle
  • 6'h15 - L2.Idle
  • 6'h16 - L2.TransmitWake
  • 6'h17 - Disabled.Entry
  • 6'h18 - Disabled.Idle
  • 6'h19 - Disabled
  • 6'h1A - Loopback.Entry
  • 6'h1B - Loopback.Active
  • 6'h1C - Loopback.Exit
  • 6'h1D - Loopback.Exit.Timeout
  • 6'h1E - HotReset.Entry
  • 6'h1F - Hot.Reset

sim_pipe_mask_tx_pll_lock

Input

Should be active during rate change. This signal Is used to mask the PLL lock signals. This interface is used only for PIPE simulations.

In serial simulations, The Endpoint PHY drives this signal. For PIPE simulations, in the Intel testbench, The PIPE BFM drives this signal.

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