L- and H-Tile Avalon® Streaming and Single Root I/O Virtualization (SR-IOV) Intel® FPGA IP for PCI Express* User Guide

ID 683111
Date 10/27/2023
Public

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Document Table of Contents

8.1.10.9. Transaction Processing Hints (TPH) Requester Enhanced Capability Header

Table 82.   Transaction Processing Hints (TPH) Requester Enhanced Capability Header Register - 0x1F8 0x1F8

Bits

Register Description

Default Value

Access

[31:20] Next Capability Pointer: Points to ATS Capability when preset, NULL otherwise. 0x0017 RO

[19:16]

Capability Version. 1

RO

[15:0]

PCI Express Extended Capability ID.

RO