Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

ID 813752
Date 8/09/2024
Public
Document Table of Contents

3.1.2. Generating the HPS Simulation Model in Platform Designer

Note: This section describes how to generate the simulation model when a single .qsys system is in the Quartus® Prime project. It does not describe the method to generate the simulation model when multiple .qsys systems are in the Quartus® Prime project. There are plans to describe this in a future version of this document.

The following steps outline how to generate the simulation model:

  1. In Quartus® Prime Pro Edition software, launch the Platform Designer and open your system design that has been created in the previous section.
  2. In Platform Designer, click on the Generate HDL button.
    Figure 32.  Platform Designer - Generate HDL... button
  3. In the Simulation section, use the “Create simulation model” dropdown list to choose “Verilog” or “VHDL”.
  4. Select which of the supported simulators to generate files. (Leaving all the boxes unselected generates files for all simulators.)
  5. Click on Generate button.
    Figure 33.  Platform Designer - Select Simulators to Generate