Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

ID 813752
Date 8/09/2024
Public
Document Table of Contents

2.2.4.1. FPGA-to-HPS

Turning on the Enable FPGA-to-HPS Interrupts option configures the HPS component to provide 64 general purpose FPGA-to-HPS interrupts, allowing soft IP in the FPGA fabric to trigger interrupts to the MPU’s generic interrupt controller (GIC). Turning on the Enable FPGA-to-HPS Interrupts option enables the fpga2hps_interrupt conduit:
  • fpga2hps_interrupt_irqFPGA-to-HPS interrupts 0 through 63
Note: If USB3.1 is enabled this interface is 63 bits wide. If USB3.1 is not enabled this interface is 64 bits wide.

The FPGA-to-HPS interrupts are asynchronous on the FPGA interface. Inside the HPS, the interrupts are synchronized to the MPU’s internal peripheral clock (mpu_periph_clk)