Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

ID 813752
Date 8/09/2024
Public
Document Table of Contents

2.2.1.6. Enable FPGA Cross Trigger Interface

The cross trigger interface (CTI) allows trigger sources and sinks in FPGA logic to interface with the embedded cross trigger (ECT).

For more information, refer to the CoreSight Debug and Trace chapter in the Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs.

If this interface must be connected to a Signal Tap instance in the FPGA fabric, then it must be left disabled in Platform Designer. Turning on the Enable CTI interface option enables the fpga_cti conduit, which is comprised of the following signals:

Table 6.   fpga_cti Signals
Signal Name Interface Type

fpga_cti_trig_in[7…0]

Conduit

fpga_cti_trig_out[7…0]

Conduit

fpga_cti_trig_in_ack[7…0]

Conduit

fpga_cti_trig_out_ack[7…0]

Conduit