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1. Introduction to the Agilex™ 5 Hard Processor System Component
2. Configuring the Agilex™ 5 Hard Processor System Component
3. Simulating the Agilex™ 5 HPS Component
4. Design Guidelines
5. HPS EMIF Platform Designer Example Designs
6. Document Revision History for the Hard Processor System Component Reference Manual Agilex™ 5 SoCs
2.1. Parameterizing the HPS Component
2.2. HPS-FPGA Interfaces
2.3. SDRAM
2.4. HPS Clocks, Reset, Power
2.5. I/O Delays
2.6. Pin Mux and Peripherals
2.7. Generating and Compiling the HPS Component
2.8. Using the Address Span Extender Component
2.9. Configuring the Agilex™ 5 Hard Processor System Component Revision History
2.2.1.1. Enable MPU Standby and Event Signals
2.2.1.2. Enable General Purpose Signals
2.2.1.3. Enable Debug APB* Interface
2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events
2.2.1.5. Enable SWJ-DP JTAG Interface
2.2.1.6. Enable FPGA Cross Trigger Interface
2.2.1.7. Enable AMBA* Trace Bus (ATB)
3.1. Simulation Flows
3.2. Running the Simulation of the Design Examples
3.3. Clock and Reset Interface
3.4. FPGA-to-HPS AXI* Subordinate Interface
3.5. FPGA-to-SDRAM AXI* Subordinate Interface
3.6. HPS-to-FPGA AXI* Initiator Interface
3.7. Lightweight HPS-to-FPGA AXI* Initiator Interface
3.8. Simulating the Agilex™ 5 HPS Component Revision History
5.1. Terminology
5.2. Block Diagram
5.3. Version Support
5.4. Download Example Design Files
5.5. HPS EMIF Platform Designer Example Designs
5.6. Specific Examples
5.7. General Connection Guideline
5.8. Supported Memory Protocols Differences Among Intel SoC Device Families
5.9. IO96 Bank and Lane Usage for HPS EMIF
5.10. Quartus Report of I/O Bank Usage
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2.4.3.2. Reset Signals
Figure 21. Platform Designer Reset Signals Sub-window
This section contains the Agilex™ 5 HPS reset signals configuration.
- Turning on the Enable HPS Warm Reset handshake signals option enables an additional pair of reset handshake signals allowing soft logic to notify the HPS when it is safe to initiate a warm reset in the FPGA fabric. Turning on this option exposes the h2f_warm_reset_handshake conduit, which is comprised of the signals h2f_warm_reset_handshake_reset_req and h2f_warm_reset_handshake_reset_ack.
- Turning on the Enable HPS-to-FPGA Cold Reset output option exposes the h2f_cold_reset reset output interface. This signal is asserted when the HPS undergoes a cold reset.
- Turning on the Enable Watchdog Reset option exposes the h2f_watchdog_reset reset output interface and is asserted when the HPS watchdog timers are triggered.
- Watchdog SDM Configuration dropdown provides an input to the compiled bitstream that directs the SDM to treat the HPS watchdog reset assertion as an HPS Cold Reset, HPS Warm Reset, or Trigger Remote Update.
For more information, refer to the HPS System Reset Considerations chapter in the Design Guidelines section.
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