Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

ID 813752
Date 8/09/2024
Public
Document Table of Contents

5.8. Supported Memory Protocols Differences Among Intel SoC Device Families

The following table describes the memory protocols supported on the HPS EMIF across the different devices.
Table 28.  Supported Memory Protocols Differences Among Intel SoC Device Families
  Agilex™ 5 D-Series SoC Agilex™ 5 E-Series SoC
Device Group Group A Group B
Example Design Name Prefix ./A5D/* ./A5ExA/* ./A5ExB/*
Protocol (for HPS EMIF) Width
DDR4

1ch x16

1ch x16+ECC

1ch x32

1ch x32+ECC

2ch x32 1

2ch x32+ECC 1

1ch x16

1ch x16+ECC

1ch x32

1ch x32+ECC

2ch x32 1

2ch x32+ECC 1

1ch x16

1ch x16+ECC

1ch x32

1ch x32+ECC

2ch x32 1

2ch x32+ECC 1

DDR5

1ch x16

1ch x16+ECC

2ch x16

1ch x32

1ch x32+ECC

2ch x32 1

2ch x32+ECC 1

1ch x16

1ch x16+ECC

2ch x16

1ch x32

1ch x32+ECC

2ch x32 1

2ch x32+ECC 1

N/A
LPDDR4/5

1ch x16

2ch x16

1ch x32

2ch x32 1

4ch x16 1

1ch x16

2ch x16

1ch x32

2ch x32 1

4ch x16 1

1ch x16

2ch x16

1ch x32

2ch x32 1

4ch x16 1

1 Uses two IOBanks (Banks 3A and 3B)