Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

ID 813752
Date 8/09/2024
Public
Document Table of Contents

2.2.1.3. Enable Debug APB* Interface

The debug Advanced Peripheral Bus ( APB* ) interface allows debug components in the FPGA fabric to access debug components in the HPS.

For more information, refer to the CoreSight Debug and Trace chapter in the Hard Processor System Technical Reference Manual: Agilex™ 5 SoCs.

Turning on this option enables the following interfaces and signals:

Table 3.   Debug APB* Signals
Signal Name Interface Type
cs_debug_apd_clock_clk

Clock Input

cs_debug_apd_reset_reset_n

Reset Input

cs_dbg_apb_paddr[16…0]

APB Requester

cs_dbg_apb_penable

APB Requester

cs_dbg_apb_prdata[31…0]

APB Requester

cs_dbg_apb_pready

APB Requester

cs_dbg_apb_psel[15…0]

APB Requester

cs_dbg_apb_pslverr

APB Requester

cs_dbg_apb_pwdata[31…0]

APB Requester

cs_dbg_apb_pwrite

APB Requester

cs_dbg_apb_dbg_apb_disable

Conduit

cs_dbg_apb_pclken

Conduit