Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

ID 813752
Date 8/09/2024
Public
Document Table of Contents

2.2.2.3. HPS to FPGA Manager

The HPS-to-FPGA AXI* 4 Manager interface allows HPS initiator to issue most data transactions to the FPGA fabric. You can use the:

  • Enable/Data Width dropdown to configure this manager interface's data widths
    • Unused
    • 128-bit
    • 64-bit
    • 32-bit
  • Interface Address Width is configurable from 38 bits down to 20 bits.
When this bridge is enabled, the interfaces hps2fpga, hps2fpga_axi_clock, and hps2fpga_axi_reset are made available.
Note: h2f_reset signal must be connected to hps2fpga_axi_reset signal for proper bridge operation.

This bridge accepts a clock input from the FPGA fabric and performs clock domain crossing internally. The exposed AXI* interface operates on the same clock domain as the clock supplied by the FPGA fabric. Other interface standards in the FPGA fabric, such as connecting to Avalon®-MM interfaces, can be supported through the use of soft logic adapters. The Platform Designer system integration tool automatically generates adapter logic to connect AXI* to Avalon®-MM interfaces.