Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

ID 813752
Date 8/09/2024
Public
Document Table of Contents

2.8. Using the Address Span Extender Component

The FPGA-to-HPS bridge memory-mapped interface can be configured to expose their entire address spaces to the FPGA fabric, 132GB and 128GB, respectively. The address span extender component provides a memory-mapped window into the address space that it manages. Using the address span extender, an FPGA manager with a smaller address span can access the entire address space exposed by the FPGA bridge.

You can use the address span extender between a soft logic manager and an FPGA-to-HPS bridge. This component reduces the number of address bits required for a manager to address a memory-mapped subordinate interface located in the HPS.

In the example shown in the figure below, the bridges in the HPS component are configured for 32-bit wide addresses (4GB address span).

Figure 31. Address Span Extender ComponentsTwo address span extender components used in a system with the HPS.

You can also use the address span extender in the HPS-to-FPGA direction, for subordinate interfaces in the FPGA. In this case, the HPS-to-FPGA bridge exposes a limited, variable address space in the FPGA, which can be paged in using the address span extender.

For example, suppose that the HPS-to-FPGA bridge has a 1-GB span, and the HPS needs to access three independent 1-GB memories in the FPGA portion of the device. To achieve this, the HPS programs the address span extender to access one SDRAM (1-GB) in the FPGA at a time. This technique is commonly called paging or windowing.

For more information, refer to the Address Span Extender Intel® FPGA IP section in the Quartus® Prime Pro Edition User Guide: Platform Designer .