Visible to Intel only — GUID: bov1686332959194
Ixiasoft
1. Introduction to the Agilex™ 5 Hard Processor System Component
2. Configuring the Agilex™ 5 Hard Processor System Component
3. Simulating the Agilex™ 5 HPS Component
4. Design Guidelines
5. HPS EMIF Platform Designer Example Designs
6. Document Revision History for the Hard Processor System Component Reference Manual Agilex™ 5 SoCs
2.1. Parameterizing the HPS Component
2.2. HPS-FPGA Interfaces
2.3. SDRAM
2.4. HPS Clocks, Reset, Power
2.5. I/O Delays
2.6. Pin Mux and Peripherals
2.7. Generating and Compiling the HPS Component
2.8. Using the Address Span Extender Component
2.9. Configuring the Agilex™ 5 Hard Processor System Component Revision History
2.2.1.1. Enable MPU Standby and Event Signals
2.2.1.2. Enable General Purpose Signals
2.2.1.3. Enable Debug APB* Interface
2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events
2.2.1.5. Enable SWJ-DP JTAG Interface
2.2.1.6. Enable FPGA Cross Trigger Interface
2.2.1.7. Enable AMBA* Trace Bus (ATB)
3.1. Simulation Flows
3.2. Running the Simulation of the Design Examples
3.3. Clock and Reset Interface
3.4. FPGA-to-HPS AXI* Subordinate Interface
3.5. FPGA-to-SDRAM AXI* Subordinate Interface
3.6. HPS-to-FPGA AXI* Initiator Interface
3.7. Lightweight HPS-to-FPGA AXI* Initiator Interface
3.8. Simulating the Agilex™ 5 HPS Component Revision History
5.1. Terminology
5.2. Block Diagram
5.3. Version Support
5.4. Download Example Design Files
5.5. HPS EMIF Platform Designer Example Designs
5.6. Specific Examples
5.7. General Connection Guideline
5.8. Supported Memory Protocols Differences Among Intel SoC Device Families
5.9. IO96 Bank and Lane Usage for HPS EMIF
5.10. Quartus Report of I/O Bank Usage
Visible to Intel only — GUID: bov1686332959194
Ixiasoft
2.7. Generating and Compiling the HPS Component
The process of generating and compiling an HPS design is very similar to the process for any other Platform Designer project. Perform the following steps:
- Generate the design with Platform Designer. The generated files include an .sdc file containing clock timing constraints. If simulation is enabled, simulation files are also generated.
- Add <qsys_system_name>.qip to the Quartus® Prime project. <qsys_system_name>.qip is the Quartus® Prime IP File for the HPS component, generated by Platform Designer.
Note: Platform Designer generates pin assignments in the .qip file.
- Perform analysis and synthesis with the Quartus® Prime software.
- Compile the design with the Quartus® Prime software.
- Optionally, back-annotate the SDRAM pin assignments, to eliminate pin assignment warnings the next time you compile the design.