Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

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ID 813752
Date 8/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to the Agilex™ 5 Hard Processor System Component 2. Configuring the Agilex™ 5 Hard Processor System Component 3. Simulating the Agilex™ 5 HPS Component 4. Design Guidelines 5. HPS EMIF Platform Designer Example Designs 6. Document Revision History for the Hard Processor System Component Reference Manual Agilex™ 5 SoCs
1. Introduction to the Agilex™ 5 Hard Processor System Component x
1.1. Micro Processor Unit 1.2. Application Processor Subsystem 1.3. Peripheral Subsystem 1.4. CoreSight* Debug Components 1.5. Interconnect 1.6. FPGA Bridges 1.7. Introduction to the Agilex™ 5 Hard Processor System Component Revision History
2. Configuring the Agilex™ 5 Hard Processor System Component x
2.1. Parameterizing the HPS Component 2.2. HPS-FPGA Interfaces 2.3. SDRAM 2.4. HPS Clocks, Reset, Power 2.5. I/O Delays 2.6. Pin Mux and Peripherals 2.7. Generating and Compiling the HPS Component 2.8. Using the Address Span Extender Component 2.9. Configuring the Agilex™ 5 Hard Processor System Component Revision History
2.2. HPS-FPGA Interfaces x
2.2.1. General 2.2.2. HPS FPGA Bridges 2.2.3. DMA Controller Interface 2.2.4. Interrupts
2.2.1. General x
2.2.1.1. Enable MPU Standby and Event Signals 2.2.1.2. Enable General Purpose Signals 2.2.1.3. Enable Debug APB* Interface 2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events 2.2.1.5. Enable SWJ-DP JTAG Interface 2.2.1.6. Enable FPGA Cross Trigger Interface 2.2.1.7. Enable AMBA* Trace Bus (ATB)
2.2.2. HPS FPGA Bridges x
2.2.2.1. FPGA to HPS Subordinate 2.2.2.2. FPGA to SDRAM Subordinate 2.2.2.3. HPS to FPGA Manager 2.2.2.4. Lightweight HPS to FPGA Manager
2.2.4. Interrupts x
2.2.4.1. FPGA-to-HPS 2.2.4.2. HPS-to-FPGA
2.3. SDRAM x
2.3.1. EMIF Interface
2.4. HPS Clocks, Reset, Power x
2.4.1. Input Clocks 2.4.2. PLL Clocks 2.4.3. Power and Resets
2.4.1. Input Clocks x
2.4.1.1. External Clocks 2.4.1.2. FPGA-to-HPS Clocks 2.4.1.3. Peripheral FPGA Clocks
2.4.2. PLL Clocks x
2.4.2.1. Main PLL Output 2.4.2.2. Peripheral PLL Output 2.4.2.3. MPU Clocks 2.4.2.4. NOC Clocks 2.4.2.5. Peripheral Clocks 2.4.2.6. HPS-to-FPGA User Clocks
2.4.3. Power and Resets x
2.4.3.1. Power Configurations 2.4.3.2. Reset Signals
2.6. Pin Mux and Peripherals x
2.6.1. Pin Mux GUI 2.6.2. EMAC PTP Interface 2.6.3. HPS I/O Open Drain 2.6.4. HPS I/O Locations
2.6.1. Pin Mux GUI x
2.6.1.1. Auto-Place IP 2.6.1.2. Advanced
2.6.1.1. Auto-Place IP x
2.6.1.1.1. Options for NAND, SDMMC, TRACE, TPIU, EMAC
2.6.1.1.1. Options for NAND, SDMMC, TRACE, TPIU, EMAC x
2.6.1.1.1.1. HPS IO Placement Priority
2.6.1.2. Advanced x
2.6.1.2.1. Advanced IP Placement 2.6.1.2.2. Advanced FPGA Placement
3. Simulating the Agilex™ 5 HPS Component x
3.1. Simulation Flows 3.2. Running the Simulation of the Design Examples 3.3. Clock and Reset Interface 3.4. FPGA-to-HPS AXI* Subordinate Interface 3.5. FPGA-to-SDRAM AXI* Subordinate Interface 3.6. HPS-to-FPGA AXI* Initiator Interface 3.7. Lightweight HPS-to-FPGA AXI* Initiator Interface 3.8. Simulating the Agilex™ 5 HPS Component Revision History
3.1. Simulation Flows x
3.1.1. Setting Up the HPS Component for Simulation 3.1.2. Generating the HPS Simulation Model in Platform Designer 3.1.3. RTL Simulation Setup Scripts
3.1.3. RTL Simulation Setup Scripts x
3.1.3.1. QuestaSim* Simulation Steps 3.1.3.2. Cadence® Xcelium* Simulation Steps 3.1.3.3. Synopsys* VCS* Simulation Steps 3.1.3.4. Synopsys* VCS* MX Simulation Steps 3.1.3.5. Aldec® Riviera-PRO* Simulation Steps
3.2. Running the Simulation of the Design Examples x
3.2.1. HPS-to-FPGA Bridge (H2F) 3.2.2. Lightweight HPS-to-FPGA (LWH2F) 3.2.3. FPGA-to-HPS Bridge (F2H) 3.2.4. FPGA-to-SDRAM Bridge (F2SDRAM)
3.2.1. HPS-to-FPGA Bridge (H2F) x
3.2.1.1. Steps to run the Simulation in Questa* Intel® FPGA Edition 3.2.1.2. Steps to run the Simulation in Synopsys* VCS*
3.2.2. Lightweight HPS-to-FPGA (LWH2F) x
3.2.2.1. Steps to run the Simulation in Questa* Intel® FPGA Edition 3.2.2.2. Steps to run the Simulation in Synopsys* VCS*
3.2.3. FPGA-to-HPS Bridge (F2H) x
3.2.3.1. Steps to run the Simulation in Questa* Intel® FPGA Edition 3.2.3.2. Steps to run the Simulation in Synopsys* VCS*
3.2.4. FPGA-to-SDRAM Bridge (F2SDRAM) x
3.2.4.1. Steps to run the Simulation in Questa* Intel® FPGA Edition 3.2.4.2. Steps to run the Simulation in Synopsys* VCS*
3.3. Clock and Reset Interface x
3.3.1. Clock Interface 3.3.2. Reset Interface
4. Design Guidelines x
4.1. HPS System Reset Considerations 4.2. Design Guidelines Revision History
5. HPS EMIF Platform Designer Example Designs x
5.1. Terminology 5.2. Block Diagram 5.3. Version Support 5.4. Download Example Design Files 5.5. HPS EMIF Platform Designer Example Designs 5.6. Specific Examples 5.7. General Connection Guideline 5.8. Supported Memory Protocols Differences Among Intel SoC Device Families 5.9. IO96 Bank and Lane Usage for HPS EMIF 5.10. Quartus Report of I/O Bank Usage
5.6. Specific Examples x
5.6.1. DDR4 Examples 5.6.2. LPDDR4 Examples 5.6.3. LPDDR5 Examples
1. Introduction to the Agilex™ 5 Hard Processor System Component
2. Configuring the Agilex™ 5 Hard Processor System Component
3. Simulating the Agilex™ 5 HPS Component
4. Design Guidelines
5. HPS EMIF Platform Designer Example Designs
6. Document Revision History for the Hard Processor System Component Reference Manual Agilex™ 5 SoCs

5.7. General Connection Guideline

The following tables generally describes how the HPS signals are connected to the HPS EMIF signals in Quartus Platform Designer.
Table 24.  1x16_1EMIF or 1x32_1EMIF configurations
Conduct HPS HPS EMIF
AXI4Lite Subordinate (b0) Io96b0_csr_axi_clk S0_axil_clk
Io96b0_csr_axi_rst S0_axil_rst_n
Io96b0_csr_axi S0_axil
AXI4 Subordinate (b0, ch0) Io96b0_ch0_axi_clk Usr_clk_0
Io96b0_ch0_axi_rst Usr_rst_n_0
Io96b0_ch0_axi S0_axi4
Table 25.  2x16_1EMIF configuration
Conduct HPS HPS EMIF
AXI4Lite Subordinate (b0) Io96b0_csr_axi_clk S0_axil_clk
Io96b0_csr_axi_rst S0_axil_rst_n
Io96b0_csr_axi S0_axil
AXI4 Subordinate (b0, ch0) Io96b0_ch0_axi_clk Usr_clk_0
Io96b0_ch0_axi_rst Usr_rst_n_0
Io96b0_ch0_axi S0_axi4
AXI4 Subordinate (b0, ch1) Io96b0_ch1_axi_clk Usr_clk_1
Io96b0_ch1_axi_rst Usr_rst_n_1
Io96b0_ch1_axi S1_axi4
Table 26.  2x32_2EMIF configuration
Conduct HPS HPS EMIF
AXI4Lite Subordinate (b0) Io96b0_csr_axi_clk S0_axil_clk
Io96b0_csr_axi_rst S0_axil_rst_n
Io96b0_csr_axi S0_axil
AXI4 Subordinate (b0, ch0) Io96b0_ch0_axi_clk Usr_clk_0
Io96b0_ch0_axi_rst Usr_rst_n_0
Io96b0_ch0_axi S0_axi4
AXI4Lite Subordinate (b1) Io96b1_csr_axi_clk S1_axil_clk
Io96b1_csr_axi_rst S1_axil_rst_n
Io96b1_csr_axi S1_axil
AXI4 Subordinate (b1, ch0) Io96b1_ch0_axi_clk Usr_clk_1
Io96b1_ch0_axi_rst Usr_rst_n_1
Io96b1_ch0_axi S1_axi4
Table 27.  4x16_2EMIF configuration
Conduct HPS HPS EMIF
AXI4Lite Subordinate (b0) Io96b0_csr_axi_clk S0_axil_clk
Io96b0_csr_axi_rst S0_axil_rst_n
Io96b0_csr_axi S0_axil
AXI4 Subordinate (b0, ch0) Io96b0_ch0_axi_clk Usr_clk_0
Io96b0_ch0_axi_rst Usr_rst_n_0
Io96b0_ch0_axi S0_axi4
AXI4 Subordinate (b0, ch1) Io96b0_ch1_axi_clk Usr_clk_1
Io96b0_ch1_axi_rst Usr_rst_n_1
Io96b0_ch1_axi S1_axi4
AXI4Lite Subordinate (b1) Io96b1_csr_axi_clk S1_axil_clk
Io96b1_csr_axi_rst S1_axil_rst_n
Io96b1_csr_axi S1_axil
AXI4 Subordinate (b1, ch0) Io96b1_ch0_axi_clk Usr_clk_2
Io96b1_ch0_axi_rst Usr_rst_n_2
Io96b1_ch0_axi S2_axi4
AXI4 Subordinate (b1, ch1) Io96b1_ch1_axi_clk Usr_clk_3
Io96b1_ch1_axi_rst Usr_rst_n_3
Io96b1_ch1_axi S3_axi4
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