Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

ID 813752
Date 8/09/2024
Public
Document Table of Contents

2.4.2.1. Main PLL Output

The default calculated PLL VCO and channel frequencies are displayed in a table. You can select the Main PLL Clock Source by the drop-down selection, HPS External Oscillator and FPGA Free Clock.

Turning on Override Main PLL Settings exposes the main PLL clocks desired frequency. You can configure the desired frequency by override the value of each of main PLL frequency.

Figure 13.  Platform Designer Main PLL Output Sub-window