Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

ID 813752
Date 8/09/2024
Public
Document Table of Contents

2.4.1.2. FPGA-to-HPS Clocks

Turning on the Enable FPGA-to-HPS Free Clock option enables the f2h_free_clk clock input. This is an alternative input to the main HPS PLL driven from the FPGA fabric instead of the dedicated hps_osc_clk pin. Turning on the Enable FPGA-to-HPS Free Clock option is subject to the same requirements as that pin.