Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

ID 813752
Date 8/09/2024
Public
Document Table of Contents

2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events

The system trace microcell hardware events interface allows logic in the FPGA to insert messages into the trace stream.

For more information, refer to the CoreSight Debug and Trace chapter in the Agilex™ 5 Hard Processor System Technical Reference Manual.

Turning on the Enable STM HW events option enables the stm_hwevents conduit, which is comprised of the following signals:

Table 4.   stm_hwevents Signals

Signal Name

Interface Type

f2h_stm_hwevents[43..0]

Conduit