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1. Introduction to the Agilex™ 5 Hard Processor System Component
2. Configuring the Agilex™ 5 Hard Processor System Component
3. Simulating the Agilex™ 5 HPS Component
4. Design Guidelines
5. HPS EMIF Platform Designer Example Designs
6. Document Revision History for the Hard Processor System Component Reference Manual Agilex™ 5 SoCs
2.1. Parameterizing the HPS Component
2.2. HPS-FPGA Interfaces
2.3. SDRAM
2.4. HPS Clocks, Reset, Power
2.5. I/O Delays
2.6. Pin Mux and Peripherals
2.7. Generating and Compiling the HPS Component
2.8. Using the Address Span Extender Component
2.9. Configuring the Agilex™ 5 Hard Processor System Component Revision History
2.2.1.1. Enable MPU Standby and Event Signals
2.2.1.2. Enable General Purpose Signals
2.2.1.3. Enable Debug APB* Interface
2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events
2.2.1.5. Enable SWJ-DP JTAG Interface
2.2.1.6. Enable FPGA Cross Trigger Interface
2.2.1.7. Enable AMBA* Trace Bus (ATB)
3.1. Simulation Flows
3.2. Running the Simulation of the Design Examples
3.3. Clock and Reset Interface
3.4. FPGA-to-HPS AXI* Subordinate Interface
3.5. FPGA-to-SDRAM AXI* Subordinate Interface
3.6. HPS-to-FPGA AXI* Initiator Interface
3.7. Lightweight HPS-to-FPGA AXI* Initiator Interface
3.8. Simulating the Agilex™ 5 HPS Component Revision History
5.1. Terminology
5.2. Block Diagram
5.3. Version Support
5.4. Download Example Design Files
5.5. HPS EMIF Platform Designer Example Designs
5.6. Specific Examples
5.7. General Connection Guideline
5.8. Supported Memory Protocols Differences Among Intel SoC Device Families
5.9. IO96 Bank and Lane Usage for HPS EMIF
5.10. Quartus Report of I/O Bank Usage
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3.1.3.2. Cadence® Xcelium* Simulation Steps
- Locate your top-level simulation model.
- You can locate it at <project directory>/<Platform Designer design name>/sim/.
- Use the name located from the previous step (step a) to replace the placeholder names TopLevel.v and TopLevel that are used in the following steps.
- Locate the Cadence® setup script.
- You can locate it at <project directory>/<Platform Designer design name>/sim/xcelium/.
- Locate xcelium_setup.sh.
- For this example, the simulator is executed in the sim/xcelium directory where the vcs_setup.sh file is located. Change directory to the sim/xcelium directory:
cd <project directory>/<Platform Designer design name>/ \ sim/xcelium/
- Copy the xcelium_setup.sh file to another file. For this exercise, it is called my_xmsim_script.sh.
cp xcelium_setup.sh my_xmsim_script.sh
- In your my_xmsim_script.sh file, delete everything except the section between the lines from "TOP-LEVEL TEMPLATE - BEGIN" to "TOP-LEVEL TEMPLATE - END".
- In your my_xmsim_script.sh file, add additional libraries and flags by adding the following lines at the top of the file:
MVCHOME=<ACDS directory>/ip/altera/mentor_vip_ae/common/ RUN_64bit=-64bit QUESTA_MVC_GCC_LIB=${MVCHOME}/questa_mvc_core/linux_x86_64_gcc-6.3_ius export LD_LIBRARY_PATH=${QUESTA_MVC_GCC_LIB}:${LD_LIBRARY_PATH}
- Uncomment the first set of lines that source xcelium_setup.sh in the template and modify to the following:
source xcelium_setup.sh \ SKIP_ELAB=1 \ SKIP_SIM=1
- Uncomment and modify the "xmvlog" line in the template:
xmvlog ../TopLevel.v
- Uncomment the second set of lines that source xcelium_setup.sh in the template and modify to the following:
source xcelium_setup.sh \ SKIP_FILE_COPY=1 \ SKIP_DEV_COM=1 \ SKIP_COM=1 \ TOP_LEVEL_NAME=TopLevel \ USER_DEFINED_ELAB_OPTIONS="-timescale\ 1ns/1ns\ -no_mixed_bus\ \ -ENABLE_BIND_WITH_COMMON_PKG" \ USER_DEFINED_SIM_OPTIONS="-sv_root\ ${QUESTA_MVC_GCC_LIB}\ -sv_lib\ \ libaxi4_IN_SystemVerilog_IUS_full_DVC"
- Save the my_xmsim_script.sh file.
- Setup your developer environment with the proper resources. Refer to Cadence® Xcelium* documentation for downloading, installing, and licensing.
- Run the simulation script:
sh my_xmsim_script.sh
- The simulation is running without any errors. Since no testbench is added, it only shows that all the HPS IP simulation files were successfully compiled and elaborated.