Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

ID 813752
Date 8/09/2024
Public
Document Table of Contents

2.4.2.2. Peripheral PLL Output

The default calculated PLL VCO and channel frequencies are displayed in a table. You can select the Peripheral PLL Clock Source by the drop-down selection, HPS External Oscillator, and FPGA Free Clock.

Turning on Override Peripheral PLL Settings exposes the peripheral PLL clocks desired frequency. You can configure the desired frequency by override the value of each of peripheral PLL frequency.

Figure 14.  Platform Designer Peripheral PLL Output Sub-window