Hard Processor System Component Reference Manual: Agilex™ 5 SoCs

ID 813752
Date 8/09/2024
Public
Document Table of Contents

2.3.1. EMIF Interface

The MPFE path is selected by checking the Enable EMIF INIU AXI* Interface to enable HPS access to the SDRAM. EMIF Topology drop-down can configure as:
  • 1x16 bit
  • 1x32 bit
  • 2x16 bit - single I096B
  • 2x32 bit
  • 4x16 bit
Warning: The AVSTx16 configuration scheme cannot be used in designs that include the HPS. HPS-EMIF signals and AVSTx16 signals are both located in the same bank, therefore, they cannot be used simultaneously. The AVSTx8 mode uses dedicated SDM I/O pins, therefore, it can be used in designs that include the HPS.