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1. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview
2. Getting Started
3. Functional Description
4. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
5. Interface Signals
6. Configuration Registers
7. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs Archives
8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
2.1. Introduction to Intel® FPGA IP Cores
2.2. Installing and Licensing Intel® FPGA IP Cores
2.3. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition)
2.4. Generated File Structure
2.5. Simulating Intel® FPGA IP Cores
2.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
2.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples
5.1. Clock and Reset Signals
5.2. Speed Selection Signal
5.3. Error Correction Signals
5.4. Avalon® Memory-Mapped Interface Programming Signals
5.5. Avalon® Streaming Data Interfaces
5.6. Avalon® Streaming Flow Control Signals
5.7. Avalon® Streaming Status Interface
5.8. PHY-side Interfaces
5.9. IEEE 1588v2 Interfaces
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5.8.1. XGMII TX Signals
Signal | Condition | Direction | Width | Description |
---|---|---|---|---|
xgmii_tx_data[] | — |
Out | 32 | 4-lane data bus. Lane 0 starts from the least significant bit.
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xgmii_tx_control[] | — |
Out | 4 | Control bits for each lane in xgmii_tx_data[].
|
xgmii_tx_valid | — |
Out | 1 | XGMII TX valid signal. When asserted, indicates that the data and control buses are valid. |
link_fault_status_xgmii_tx_data[] | — | In | 2 | This signal is present in the MAC TX only variation. Connect this signal to the corresponding RX client logic to handle the local and remote faults. The following values indicate the link fault status:
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