Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813663
Date 7/08/2024
Public
Document Table of Contents

3.9.3. RX Datapath

In the RX datapath, the IEEE 1588v2 feature provides a timestamp for all receive frames. The timestamp is aligned with the avalon_st_rx_startofpacket signal.