Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813663
Date 7/08/2024
Public
Document Table of Contents

3.1. Architecture

The Low Latency Ethernet 10G MAC Intel® FPGA IP core is a composition of the following blocks: MAC receiver (MAC RX), MAC transmitter (MAC TX), configuration and status registers, and clock and reset.

Figure 7.  Low Latency Ethernet 10G MAC Block Diagram