Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813663
Date 7/08/2024
Public
Document Table of Contents

5.9.3. IEEE 1588v2 Interface Clocks

Table 31.  Clock Signals for the IEEE 1588V2 Interfaces
Interface Signal Speed Clock Signal

tx_egress_*

tx_etstamp_ins_*

10M/100M/1G/2.5G/5G/10G(USXGMII) tx_312_5_clk

1G/2.5G

10M/100M/1G/2.5G

tx_156_25_clk

tx_time_of_day_*_10G_*

10M/100M/1G/2.5G/5G/10G(USXGMII) tx_312_5_clk

1G/2.5G

10M/100M/1G/2.5G

tx_time_of_day_*_1G_*

10M/100M/1G/2.5G/5G/10G(USXGMII)

1G/2.5G

10M/100M/1G/2.5G

gmii_tx_clk

rx_ingress_*

rx_estamp_ins_*

10M/100M/1G/2.5G/5G/10G(USXGMII) rx_312_5_clk

1G/2.5G

10M/100M/1G/2.5G

rx_156_25_clk

rx_time_of_day_*_10G_*

10M/100M/1G/2.5G/5G/10G(USXGMII) rx_312_5_clk

1G/2.5G

10M/100M/1G/2.5G

rx_time_of_day_*_1G_*

10M/100M/1G/2.5G/5G/10G(USXGMII)

1G/2.5G

10M/100M/1G/2.5G

gmii_rx_clk