Visible to Intel only — GUID: yjg1709696902050
Ixiasoft
Visible to Intel only — GUID: yjg1709696902050
Ixiasoft
6.10. Timestamp Registers
Word Offset | Register Name | Description | Access | HW Reset Value |
---|---|---|---|---|
0x0100 | tx_period_10g | Specifies the clock period for the timestamp adjustment on the transmit datapaths when operating at 10G PHY speed. The MAC IP core multiplies the value of this register by the number of stages separating the actual timestamp and XGMII bus.
|
RW | 0x33333 |
0x0102 | tx_fns_adjustment_10G | Static timing adjustment in fractional nanoseconds on the transmit datapaths when operating at 10G and 10M/100M/1G/2.5G/5G/10G (USXGMII) operations.
Configure this register before you enable the MAC IP core for operations. For timing adjustment calculations, refer to the related links. |
RW | 0x0 |
0x0104 | tx_ns_adjustment_10G | Static timing adjustment in nano seconds on the transmit datapaths for 10G and 10M/100M/1G/2.5G/5G/10G (USXGMII) speed.
Configure this register before you enable the MAC IP core for operations. For timing adjustment calculations, refer to the related links. |
RW | 0x0 |
0x0108 | tx_period_mult_speed | Specifies the clock period for the timestamp adjustment on the transmit datapaths when operating at 10M/100M/1G/2.5G speed of MII/GMII. The MAC IP core multiplies the value of this register by the number of stages separating the actual timestamp and MII/GMII bus.
The IP core automatically sets the clock period for 1G/2.5G configurations. For 1G, the clock period is set to 16 ns for 62.5 MHz clock. For 2.5G, the clock period is 6.4 ns for 156.25 MHz clock. |
RW | 0x80000 |
0x010A | tx_fns_adjustment_mult_speed | Static timing adjustment in fractional nanoseconds on the datapaths for 10M/100M/1G/2.5G operations.
Configure this register before you enable the MAC IP core for operations. For timing adjustment calculations, refer to the related links. |
RW | 0x0 |
0x010C | tx_ns_adjustment_mult_speed | Static timing adjustment in nanoseconds on the datapaths for 10M/100M/1G/2.5G operations.
Configure this register before you enable the MAC IP core for operations. For timing adjustment calculations, refer to the related links. |
RW | 0x0 |
0x110 | tx_asymmetry | Specifies the asymmetry value and direction of arithmetic operation.
|
RW | 0x0 |
0x112 | tx_p2p | Specifies the direction of arithmetic operation for meanPathDelay.
|
RW | 0x0 |
0x114 | tx_cf_err_stat |
|
RW1C | 0x0 |
0x0120 | rx_period_10g | Specifies the clock period for the timestamp adjustment on the receive datapaths for 10G and 10M/100M/1G/2.5G/5G/10G (USXGMII) speed. The MAC IP core multiplies the value of this register by the number of stages separating the actual timestamp and XGMII bus.
|
RW | 0x33333 |
0x0122 | rx_fns_adjustment_10G | Static timing adjustment in fractional nanoseconds on the receive datapaths for 10G and 10M/100M/1G/2.5G/5G/10G (USXGMII) speed..
|
RW | 0x0 |
0x0124 | rx_ns_adjustment_10G | Static timing adjustment in nanoseconds on the receive datapaths when operating at 10G speed.
|
RW | 0x0 |
0x0128 | rx_period_mult_speed | Specifies the clock period for the timestamp adjustment on the receive datapaths when operating at 10M/100M/1G/2.5G speed. The MAC IP core multiplies the value of this register by the number of stages separating the actual timestamp and GMII bus.
The IP core automatically sets the clock period for 1G/2.5G configurations. For 1G, the clock period is set to 16 ns for 62.5 MHz clock. For 2.5G, the clock period is 6.4 ns for 156.25 MHz clock. |
RW | 0x80000 |
0x012A | rx_fns_adjustment_mult_speed | Static timing adjustment in fractional nanoseconds on the receive datapaths for 10M/100M/1G/2.5G speed.
Configure this register before you enable the MAC IP core for operations. For timing adjustment calculations, refer to the related links. |
RW | 0x0 |
0x012C | rx_ns_adjustment_mult_speed | Static timing adjustment in nanoseconds on the receive datapaths for 10M/100M/1G/2.5G speed.
Configure this register before you enable the MAC IP core for operations. For timing adjustment calculations, refer to the related links. |
RW | 0x0 |
0x12E | rx_p2p_mpd_ns | meanPathDelay valid and value in ns. The peer-to-peer mechanism delivers meanPathDelay for each ingress port. This needs to be added to the Sync packet’s correction field before the packet is sent out on egress port. Thus, the egress port might add any of the ingress ports' 'meanPathDelay'. The value to be added at the egress port should correspond to the ingress port on which the Sync packet has arrived.
|
RW | 0x0 |
0x130 | rx_p2p_mpd_fns | meanPathDelay value in fns.
|
RW | 0x0 |