Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813663
Date 7/08/2024
Public
Document Table of Contents

1.5.1. Resource Utilization

The estimated resource utilization for all operating modes are obtained by compiling the Low Latency Ethernet 10G MAC Intel® FPGA IP core with the Quartus® Prime software targeting on Agilex™ 5 devices. These estimates are generated by the fitter, excluding the virtual I/Os.

Table 4.  Resource Utilization for LL Ethernet 10G MAC for Agilex™ 5 Devices
MAC Settings ALMs ALUTs Logic Registers Memory Block (M20K)
Operating Mode Enabled Options
1G/2.5G

Supplementary addresses.

Memory-based statistics counters.

3300 4500 5750 4
1G/2.5G

IEEE 1588 PTP supplementary addresses.

Memory-based statistics counters.

Time of day: 96b and 64b. 5200 7200 11200 21
10M/100M/1G/2.5G/5G/10G (USXGMII)

Supplementary addresses.

Memory-based statistics counters.

2900 4300 4700 4
10M/100M/1G/2.5G/5G/10G (USXGMII)

IEEE 1588 PTP supplementary addresses.

Memory-based statistics counters.

Time of day: 96b and 64b. 5200 6000 8200 21
10M/100M/1G/2.5G

Supplementary addresses.

Memory-based statistics counters.

3400 4725 6000 4