Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813663
Date 7/08/2024
Public
Document Table of Contents

5.9.2. IEEE 1588v2 Ingress RX Signals

The signals below are present when you select the Enable time stamping option.

Table 30.  IEEE 1588v2 Ingress RX Signals
Signal Direction Width Description
rx_ingress_timestamp_96b_valid Out 1 When asserted, this signal checks for a valid timestamp on rx_ingress_timestamp_96b_data[]. The MAC IP core asserts this signal in the same clock cycle it asserts avalon_st_rx_startofpacket.
rx_ingress_timestamp_96b_data[] Out 96 Carries the 96-bit ingress timestamp in the following format:
  • Bits 48 to 95: 48-bit seconds field
  • Bits 16 to 47: 32-bit nanoseconds field
  • Bits 0 to 15: 16-bit fractional nanoseconds field
rx_ingress_timestamp_64b_valid Out 1 When asserted, this signal checks for a valid timestamp on rx_ingress_timestamp_64b_data[]. The MAC IP core asserts this signal in the same clock cycle it asserts avalon_st_rx_startofpacket.
rx_ingress_timestamp_64b_data[] Out 64 Carries the 64-bit ingress timestamp in the following format:
  • Bits 16 to 63: 48-bit nanoseconds field
  • Bits 0 to 15: 16-bit fractional nanoseconds field

rx_time_of_day_96b_10g_data

rx_time_of_day_96b_1g_data

In 96 Carries the time-of-day (TOD) from an external TOD module to the MAC IP core in the following format:
  • Bits 48 to 95: 48-bit seconds field
  • Bits 16 to 47: 32-bit nanoseconds field
  • Bits 0 to 15: 16-bit fractional nanoseconds field

rx_time_of_day_64b_10g_data

rx_time_of_day_96b_1g_data

In 64 Carries the TOD from an external TOD module the MAC IP core in the following format:
  • Bits 16 to 63: 48-bit nanoseconds field
  • Bits 0 to 15: 16-bit fractional nanoseconds field
rx_path_delay_10g_data[15:0] In 16 Connect this bus to the PHY Intel® FPGA IP. This bus carries the path delay (residence time), measured between the physical network and the PHY side of the MAC IP Core (XGMII, GMII, or MII). The MAC IP core uses this value when generating the ingress timestamp to account for the delay. The path delay is in the following format:
  • Bits 0 to 9: Fractional number of clock cycle
  • Bits 10 to 15/23: Number of clock cycle
rx_path_delay_10g_data[23:0] (for USXGMII speed mode) In 24

rx_path_delay_1g_data[21:0]

In 22 Connect this bus to the PHY Intel® FPGA IP. This bus carries the path delay, which is measured between the physical network and the PHY side of the MAC IP Core (GMII or MII). The MAC IP core uses this value when generating the ingress timestamp to account for the delay. The path delay is in the following format:
  • Bits 0 to 9: Fractional number of clock cycle
  • Bits 10 to 21: Number of clock cycle
rx_ingress_p2p_val[] Out 46 Represents <meanPathDelay> for the current ingress port, which is used for peer-to-peer operations.
  • Bits 16 to 45: Link delay in nanoseconds field
  • Bits 0 to 15: Link delay in fractional nanoseconds field
rx_ingress_p2p_val_valid Out 1 When asserted, this signal indicates the rx_ingress_p2p_val is valid.