Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813663
Date 7/08/2024
Public
Document Table of Contents

3.5.9. RX Timing Diagrams

Figure 21. Back-to-back Transmission of Normal Frames with CRC Removal EnabledThe following diagram shows back-to-back reception of normal frames with CRC removal enabled.


Figure 22. Back-to-back Transmission of Normal Frames with Preamble Passthrough Mode EnabledThe following diagram shows back-to-back reception of normal frames with preamble passthrough mode and padding bytes and CRC removal enabled.