Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813663
Date 7/08/2024
Public
Document Table of Contents

1.5.2. TX and RX Latency

The TX and RX latency values are based on the following definitions and assumptions:

  • TX latency is the time taken for the data frame to move from the Avalon® streaming interface to the PHY-side interface.
  • RX latency is the time taken for the data frame to move from the PHY-side interface to the Avalon® streaming interface.
  • No backpressure on the Avalon® streaming TX and RX interfaces.
  • All options under Legacy Ethernet 10G MAC interfaces, that allow compatibility with the legacy MAC are disabled.
Table 5.  TX and RX Latency Values for Agilex™ 5 DevicesThese latency values are MAC-only latencies and do not include the PHY latencies.
MAC Operating Mode Speed Latency (ns)
TX RX Total
1G/2.5G 1 Gbps 235.2 222.4 457.6
1G/2.5G 2.5 Gbps 140.8 121.7 262.5
10M/100M/1G/2.5G/5G/10G (USXGMII) 10 Gbps 25.6 41.6 67.2
10M/100M/1G/2.5G/5G/10G (USXGMII) 5 Gbps 38.4 67.2 105.6
10M/100M/1G/2.5G/5G/10G (USXGMII) 2.5 Gbps 64 118.4 182.4
10M/100M/1G/2.5G/5G/10G (USXGMII) 1 Gbps 121.6 272 393.6
10M/100M/1G/2.5G/5G/10G (USXGMII) 100 Mbps 1238.4 2576 3814.4
10M/100M/1G/2.5G/5G/10G (USXGMII) 10 Mbps 12121.6 25616 37737.6
10M/100M/1G/2.5G 100 M 1350 1665.8 3015.8
10M/100M/1G/2.5G 10 M 11553 17665.8 29218.8