Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813663
Date 7/08/2024
Public
Document Table of Contents

3.5.5.1. Frame Length

The frame length must be at least 64 (0x40) bytes and not exceed the following maximum value for the different frame types:

  • Basic—The value in the rx_frame_maxlength register.
  • VLAN tagged—The value in the rx_frame_maxlength register plus four bytes when the rx_vlan_detection[0] register bit is 0; or the value in the rx_frame_maxlength register when the rx_vlan_detection[0] register bit is set to 1.
  • Stacked VLAN tagged—The value in the rx_frame_maxlength register plus eight bytes when the rx_vlan_detection[0] register bit is 0; or the value in the rx_frame_maxlength register when the rx_vlan_detection[0] register bit is set to 1.

The following error bits represent frame length violations:

  • avalon_st_rx_error[2]—undersized frames.
  • avalon_st_rx_error[3]—oversized frames.