Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813663
Date 7/08/2024
Public
Document Table of Contents

5.8.1. XGMII TX Signals

Table 24.  XGMII Transmit Signals
Signal Condition Direction Width Description
xgmii_tx_data[]

Out 32

4-lane data bus. Lane 0 starts from the least significant bit.

  • Lane 0: xgmii_tx_data[7:0]
  • Lane 1: xgmii_tx_data[15:8]
  • Lane 2: xgmii_tx_data[23:16]
  • Lane 3: xgmii_tx_data[31:24]
xgmii_tx_control[]

Out 4

Control bits for each lane in xgmii_tx_data[].

  • Lane 0: xgmii_tx_control[0]
  • Lane 1: xgmii_tx_control[1]
  • Lane 2: xgmii_tx_control[2]
  • Lane 3: xgmii_tx_control[3]
xgmii_tx_valid

Out 1 XGMII TX valid signal. When asserted, indicates that the data and control buses are valid.
link_fault_status_xgmii_tx_data[] In 2 This signal is present in the MAC TX only variation. Connect this signal to the corresponding RX client logic to handle the local and remote faults. The following values indicate the link fault status:
  • 0x0: No link fault
  • 0x1: Local fault
  • 0x2: Remote fault