Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813663
Date 7/08/2024
Public
Document Table of Contents

5.8.5. Clock Enable Signals

For 10M/100M/1G/2.5G variant, only tx_clkena & rx_clkena signals are available.
Table 28.  Clock Enable Signals
Signal Direction Width Description
tx_clkena In 1

For 10M/100M/1G/2.5G variant, this clock effectively divides gmii16b_tx_clk to 6.25 MHz for 100 Mbps and 0.625 MHz for 10 Mbps.

rx_clkena In 1

For 10M/100M/1G/2.5G variants, this clock effectively divides gmii16b_rx_clk to 6.25 MHz for 100 Mbps and 0.625 MHz for 10 Mbps.