Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813663
Date 7/08/2024
Public
Document Table of Contents

4. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core

You customize the Intel® FPGA IP core by specifying the parameters on the parameter editor in the Quartus® Prime software. The parameter editor enables only the parameters that are applicable to the selected speed.

Table 13.  Low Latency Ethernet 10G MAC Intel® FPGA IP Core Parameters
Parameter Value Description
Speed 1G/2.5G, 10M/100M/1G/2.5G/5G/10G (USXGMII), 10M/100M/1G/2.5G Select the desired speed.
Datapath options TX & RX Select the MAC variation to instantiate.
  • TX & RX—instantiates both MAC TX and RX.
Enable ECC on memory blocks On, Off Turn on this option to enable error detection and correction on memory blocks.
Enable preamble pass-through mode On, Off

Turn on this option to enable preamble pass-through mode. You must also set the tx_preamble_control, rx_preamble_control, and rx_custom_preamble_forward registers to 1. When enabled, the IP core allows custom preamble in data frames on the transmit and receive datapaths.

This option is available only for 10G speed of the 10M/100M/1G/2.5G/5G/10G (USXGMII) variant .

Enable priority-based flow control (PFC) On, Off

Turn on this option to enable PFC. You must also set the tx_pfc_priority_enable[n]bit to 1 and specify the number of priority queues in the Number of PFC queues field.

This option is available only for 10G speed of the 10M/100M/1G/2.5G/5G/10G (USXGMII) variant.

Number of PFC queues 2—8 Specify the number of PFC queues. This option is only enabled if you turn Enable priority-based flow control (PFC).
Enable supplementary address On, Off Turn on this option to enable supplementary addresses. You must also set the EN_SUPP0/1/2/3 bits in the rx_frame_control register to 1.
Enable statistics collection On, Off Turn on this option to collect statistics on the TX and RX datapaths.
Statistics counters Memory-based, Register-based Specify the implementation of the statistics counters. When you turn on Statistics collection, the default implementation of the counters is Memory-based.
  • Memory-based—selecting this option frees up logic elements. The MAC IP core does not clear memory-based counters after they are read.
  • Register-based—selecting this option frees up the memory. The MAC IP core clears register-based statistic counters after the counters are read.

Memory-based statistics counters may not be accurate when the MAC IP core receives or transmits back-to-back undersized frames. On the TX datapath, you can enable padding to avoid this situation. Undersized frames are frames with less than 64 bytes.

TX and RX datapath Reset/Default to Enable On, Off Turn off this option to disable TX and RX datapath during startup or CSR reset.
Enable time stamping On, Off Turn on this option to enable time stamping on the TX and RX datapaths.
Enable PTP one-step clock support On, Off Turn on this option to enable 1-step time stamping.
Enable asymmetry support On, Off Turn on this option to enable asymmetry support on TX datapath. This option is enabled only when you turn on time stamping and PTP one-step clock support.
Enable peer-to-peer On, Off Turn on this option to enable peer-to-peer support on TX datapath. This option is enabled only when you turn on time stamping and PTP one-step clock support. This option is not available in 10M/100M/1G/2.5G, and 10M/100M/1G/2.5G/10G configurations.
Timestamp fingerprint width 1–32 Specify the width of the timestamp fingerprint in bits on the TX path.
Time of Day Format Enable 96b Time of Day Format only, Enable 64b Time of Day Format only, Enable both 96b and 64b Time of Day Format

Specify the time-of-day format.

Use legacy Ethernet 10G MAC Avalon® memory-mapped interface On, Off Turn on this option to maintain compatibility with the 64-bit Ethernet 10G MAC on the Avalon® memory-mapped interface. This option is not available in 1G/2.5G and 10M/100M/1G/2.5G configurations.
Use legacy Ethernet 10G MAC Avalon® streaming interface On, Off Turn on this option to maintain compatibility with the 64-bit Ethernet 10G MAC on the Avalon® streaming interface. This option is not available in 1G/2.5G and 10M/100M/1G/2.5G configurations.