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1. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview
2. Getting Started
3. Functional Description
4. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
5. Interface Signals
6. Configuration Registers
7. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs Archives
8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
2.1. Introduction to Intel® FPGA IP Cores
2.2. Installing and Licensing Intel® FPGA IP Cores
2.3. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition)
2.4. Generated File Structure
2.5. Simulating Intel® FPGA IP Cores
2.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
2.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples
5.1. Clock and Reset Signals
5.2. Speed Selection Signal
5.3. Error Correction Signals
5.4. Avalon® Memory-Mapped Interface Programming Signals
5.5. Avalon® Streaming Data Interfaces
5.6. Avalon® Streaming Flow Control Signals
5.7. Avalon® Streaming Status Interface
5.8. PHY-side Interfaces
5.9. IEEE 1588v2 Interfaces
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6.10.3. PTP Register Configuration
Perform the following steps once after power up or link down event to calculate TX and RX datapath delay:
- Wait until the link is up and stable.
- Wait until tx_measure_valid and rx_measure_valid from 1G/2.5G/5G/10G Multirate Ethernet PHY IP register 0x420 are valid.
- For 1G/2.5G (MGBASE), the valid status are at register offset 0x17, bit 0 and bit 1.
- For 10M/100M/1G/2.5G/5G/10G (USXGMII), the valid status are at register offset 0x420, bit 0 and it 1.
- Read TX and RX datapath deterministic latency values from the Multi-rate Ethernet PHY IP and calculate TX/RX latency. Refer to Calculating Deterministic Latency.
- For 1G/2.5G (MGBASE), the TX DL latency value is at register offset 0x18 and 0x19 while the RX DL latency value is at register offset 0x1B and 0x1A.
- For 10M/100M/1G/2.5G/5G/10G (USXGMII), the TX DL latency value is at register offset 0x421 while the RX DL latency value is at register offset 0x422.
- Convert the latency values to 16-bit nanoseconds and 16-bit fractional nanoseconds by multiplying the values by 216 or 65536.
- Calculate the sum of the TX/RX DL latency values and the TX/RX PMA delay values (In nanoseconds and fractional nanoseconds).
- Write the calculated 16-bit values to the TX and RX latency registers of the Low Latency Ethernet 10G MAC:
For 1G/2.5G (MGBASE):
- Write the lower 16-bit TX values to 0x10A register (TX fns value).
- Write the upper 16-bit TX values to 0x10C register (TX ns value).
- Write the lower 16-bit RX values to 0x12A register (RX fns value).
- Write the upper 16-bit RX values to 0x12C register (RX ns value).
For 10M/100M/1G/2.5G/5G/10G (USXGMII):- Write the lower 16-bit TX values to 0x0102 register (TX fns value).
- Write the upper 16-bit TX values to 0x0104 register (TX ns value).
- Write the lower 16-bit RX values to 0x0122 register (RX fns value).
- Write the upper 16-bit RX values to 0x0124 register (RX ns value).