Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813663
Date 7/08/2024
Public
Document Table of Contents

5.8.2. XGMII RX Signals

Table 25.  XGMII Receive Signals
Signal Condition Direction Width Description
xgmii_rx_data[]

In 32 4-lane RX data bus. Lane 0 starts from the least significant bit.
  • Lane 0: xgmii_rx_data[7:0]
  • Lane 1: xgmii_rx_data[15:8]
  • Lane 2: xgmii_rx_data[23:16]
  • Lane 3: xgmii_rx_data[31:24]
xgmii_rx_control[]

In 4 Control bits for each lane in xgmii_rx_data[].
  • Lane 0: xgmii_rx_control[0]
  • Lane 1: xgmii_rx_control[1]
  • Lane 2: xgmii_rx_control[2]
  • Lane 3: xgmii_rx_control[3]
xgmii_rx_valid

In 1 XGMII RX valid signal. When asserted, indicates that the data and control buses are valid.
link_fault_status_xgmii_rx_data[] Out 2 The following values indicate the link fault status:
  • 0x0 = No link fault
  • 0x1 = Local fault
  • 0x2 = Remote fault