Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813663
Date 7/08/2024
Public
Document Table of Contents

5.8.4. GMII RX Signals

Table 27.  GMII RX Signals
Signal Operating Mode Direction Width Description
gmii16b_rx_clk
  • 1G/2.5G (MGBASE)
  • 10M/100M/1G/2.5G (MGBASE)
In 1 156.25 MHz RX clock for 2.5G; 62.5 MHz RX clock for 1G; 62.5 MHz RX clock for 10M/100M/1G.
gmii16b_rx_d[] In 16 RX data.
gmii16b_rx_dv In 2 When asserted, indicates the RX data is valid.
gmii16b_rx_err In 2 When asserted, indicates the RX data contains error.