Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813663
Date 7/08/2024
Public
Document Table of Contents

3.9.4.2. PTP Packet over UDP/IPv4

The following figures show the structure and format of the PTP packet encapsulated in UDP/IPv4. Checksum calculation is optional for the UDP/IPv4 protocol. The 1588v2 TX logic should set the checksum to zero.

Figure 30. PTP packet within UDP over IPv4 over Ethernet Frame
Figure 31. PTP Packet Format over UDP/IPv4