Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813663
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview 2. Getting Started 3. Functional Description 4. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 5. Interface Signals 6. Configuration Registers 7. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs Archives 8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview x
1.1. Features 1.2. Release Information 1.3. Low Latency Ethernet 10G MAC Operating Modes 1.4. Device Family Support 1.5. Performance and Resource Utilization
1.5. Performance and Resource Utilization x
1.5.1. Resource Utilization 1.5.2. TX and RX Latency
2. Getting Started x
2.1. Introduction to Intel® FPGA IP Cores 2.2. Installing and Licensing Intel® FPGA IP Cores 2.3. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) 2.4. Generated File Structure 2.5. Simulating Intel® FPGA IP Cores 2.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 2.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples
2.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core x
2.6.1. Design Considerations
2.6.1. Design Considerations x
2.6.1.1. Timing Constraints
2.6.1.1. Timing Constraints x
2.6.1.1.1. Pseudo-Static CSR Fields 2.6.1.1.2. Clock Crosser 2.6.1.1.3. Dual Clock FIFO
2.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples x
2.7.1. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example for Agilex™ 5 Devices
3. Functional Description x
3.1. Architecture 3.2. Interfaces 3.3. Frame Types 3.4. TX Datapath 3.5. RX Datapath 3.6. Flow Control 3.7. Reset Requirements 3.8. XGMII Error Handling (Link Fault) 3.9. IEEE 1588v2
3.4. TX Datapath x
3.4.1. Padding Bytes Insertion 3.4.2. Address Insertion 3.4.3. CRC-32 Insertion 3.4.4. XGMII Encapsulation 3.4.5. Inter-Packet Gap Generation and Insertion 3.4.6. XGMII Transmission 3.4.7. TX Promiscuous (Transparent) Mode 3.4.8. TX Timing Diagrams
3.5. RX Datapath x
3.5.1. XGMII Decapsulation 3.5.2. CRC Checking 3.5.3. Address Checking 3.5.4. Frame Type Checking 3.5.5. Length Checking 3.5.6. CRC and Padding Bytes Removal 3.5.7. Overflow Handling 3.5.8. RX Promiscuous (Transparent) Mode 3.5.9. RX Timing Diagrams
3.5.5. Length Checking x
3.5.5.1. Frame Length 3.5.5.2. Payload Length
3.6. Flow Control x
3.6.1. IEEE 802.3 Flow Control 3.6.2. Priority-Based Flow Control
3.6.1. IEEE 802.3 Flow Control x
3.6.1.1. Pause Frame Reception 3.6.1.2. Pause Frame Transmission
3.6.2. Priority-Based Flow Control x
3.6.2.1. PFC Frame Reception 3.6.2.2. PFC Frame Transmission
3.9. IEEE 1588v2 x
3.9.1. Architecture 3.9.2. TX Datapath 3.9.3. RX Datapath 3.9.4. Frame Format
3.9.4. Frame Format x
3.9.4.1. PTP Packet in IEEE 802.3 3.9.4.2. PTP Packet over UDP/IPv4 3.9.4.3. PTP Packet over UDP/IPv6
5. Interface Signals x
5.1. Clock and Reset Signals 5.2. Speed Selection Signal 5.3. Error Correction Signals 5.4. Avalon® Memory-Mapped Interface Programming Signals 5.5. Avalon® Streaming Data Interfaces 5.6. Avalon® Streaming Flow Control Signals 5.7. Avalon® Streaming Status Interface 5.8. PHY-side Interfaces 5.9. IEEE 1588v2 Interfaces
5.5. Avalon® Streaming Data Interfaces x
5.5.1. Avalon® Streaming TX Data Interface Signals 5.5.2. Avalon® Streaming RX Data Interface Signals 5.5.3. Avalon® Streaming Data Interface Clocks
5.7. Avalon® Streaming Status Interface x
5.7.1. Avalon® Streaming Interface TX Status Signals 5.7.2. Avalon® Streaming Interface RX Status Signals
5.8. PHY-side Interfaces x
5.8.1. XGMII TX Signals 5.8.2. XGMII RX Signals 5.8.3. GMII TX Signals 5.8.4. GMII RX Signals 5.8.5. Clock Enable Signals
5.9. IEEE 1588v2 Interfaces x
5.9.1. IEEE 1588v2 Egress TX Signals 5.9.2. IEEE 1588v2 Ingress RX Signals 5.9.3. IEEE 1588v2 Interface Clocks
6. Configuration Registers x
6.1. Register Map 6.2. Register Access Definition 6.3. Primary MAC Address 6.4. MAC Reset Control Register 6.5. TX Configuration and Status Registers 6.6. Flow Control Registers 6.7. RX Configuration and Status Registers 6.8. ECC Registers 6.9. Statistics Registers 6.10. Timestamp Registers
6.10. Timestamp Registers x
6.10.1. Calculating PHY Total Latency 6.10.2. Calculating Deterministic Latency 6.10.3. PTP Register Configuration
1. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview
2. Getting Started
3. Functional Description
4. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
5. Interface Signals
6. Configuration Registers
7. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs Archives
8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

5.9.1. IEEE 1588v2 Egress TX Signals

The signals below are present when you select the Enable time stamping option.

Table 29.  IEEE 1588v2 Egress TX Signals
Signal Direction Width Description
tx_egress_timestamp_request_valid In 1 Assert this signal to request for a timestamp for the transmit frame. This signal must be asserted in the same clock cycle avalon_st_tx_startofpacket is asserted.
tx_egress_timestamp_request_fingerprint[n-1:0] In n n = value of the Timestamp fingerprint width parameter.

Use this bus to specify the fingerprint of the transmit frame that you are requesting a timestamp for. This bus must carry a valid fingerprint at the same time tx_egress_timestamp_request_valid is asserted.

The purpose of the fingerprint is to associate the timestamp with the packet. Thus, it can be the sequence ID field from the PTP packet or some other unique field of the packet, to validate both the fingerprint and timestamp collected from the CPU.

tx_egress_timestamp_96b_valid Out 1 When asserted, this signal qualifies the timestamp on tx_egress_timestamp_96b_data[] for the transmit frame whose fingerprint is specified by tx_egress_timestamp_96b_fingerprint[] .
tx_egress_timestamp_96b_data[95:0] Out 96 Carries the 96-bit egress timestamp in the following format:
  • For 1588v2 format:
    • Bits 48 to 95: 48-bit seconds field
    • Bits 16 to 47: 32-bit nanoseconds field
    • Bits 0 to 15: 16-bit fractional nanoseconds field
  • For 1588v1 format:
    • Bits 64 to 95: 32-bit seconds field
    • Bits 32 to 63: 32-bit nanoseconds field
    • Bits 0 to 31: Unused
tx_egress_timestamp_96b_fingerprint[n-1:0] Out n n = value of the Timestamp fingerprint width parameter.

The fingerprint of the transmit frame, which is received on tx_egress_timestamp_request_data[]. This fingerprint specifies the transmit frame the egress timestamp on tx_egress_timestamp_96b_data[] is for.

tx_egress_timestamp_64b_valid Out 1 When asserted, this signal qualifies the timestamp on tx_egress_timestamp_64b_data[] for the transmit frame whose fingerprint is specified by tx_egress_timestamp_64b_fingerprint[].
tx_egress_timestamp_64b_data[63:0] Out 64 Carries the 64-bit egress timestamp in the following format:
  • Bits 16 to 63: 48-bit nanoseconds field
  • Bits 0 to 15: 16-bit fractional nanoseconds field
tx_egress_timestamp_64b_fingerprint[n-1:0] Out n n = value of the Timestamp fingerprint width parameter.

The fingerprint of the transmit frame, which is received on tx_egress_timestamp_request_data[]. This fingerprint specifies the transmit frame the egress timestamp on tx_egress_timestamp_64b_data[] signal is for.

tx_egress_p2p_update In 1

Assert this signal when the CF needs to be added with <meanPathDelay> given by tx_egress_p2p_val for a transmit frame, as part of peer-to-peer mechanism.

Assert this signal in the same clock cycle as the start of packet (avalon_st_tx_startofpacket is asserted).

tx_egress_p2p_val[45:0] In 46

This represents <meanPathDelay> for peer to peer operations.

  • Bits 16 to 45: Link delay in nanoseconds field
  • Bits 0 to 15: Link delay in fractional nanoseconds field
tx_etstamp_ins_ctrl_timestamp_insert In 1 Assert this signal to insert egress timestamp into the associated frame. Assert this signal in the same clock cycle avalon_st_tx_startofpacket is asserted.
tx_etstamp_ins_ctrl_timestamp_format In 1 Use this signal to specify the format of the timestamp to be inserted.
  • 0: 1588v2 format (48-bits second field + 32-bits nanosecond field + 16-bits correction field for fractional nanosecond). Required offset location of timestamp and correction field.
  • 1: 1588v1 format (32-bits second field + 32-bits nanosecond field). Required offset location of timestamp.

Assert this signal in the same clock cycle as the start of packet (avalon_st_tx_startofpacket is asserted).

tx_etstamp_ins_ctrl_residence_time_update In 1 Assert this signal to add residence time (egress timestamp –ingress timestamp) into correction field of PTP frame. Required offset location of correction field. Assert this signal in the same clock cycle as the start of packet (avalon_st_tx_startofpacket is asserted).
tx_etstamp_ins_ctrl_ingress_timestamp_96b[95:0] In 96 96-bit format of ingress timestamp.(48 bits second + 32 bits nanosecond + 16 bits fractional nanosecond). Assert this signal in the same clock cycle as the start of packet (avalon_st_tx_startofpacket is asserted).
tx_etstamp_ins_ctrl_ingress_timestamp_64b[63:0] In 64 64-bit format of ingress timestamp. (48-bits nanosecond + 16-bits fractional nanosecond). Assert this signal in the same clock cycle as the start of packet (avalon_st_tx_startofpacket is asserted).
tx_etstamp_ins_ctrl_residence_time_calc_format In 1 Format of timestamp to be used for residence time calculation.
  • 0: 96-bits (96-bits egress timestamp - 96-bits ingress timestamp).
  • 1: 64-bits (64-bits egress timestamp - 64-bits ingress timestamp).
Assert this signal in the same clock cycle as the start of packet (avalon_st_tx_startofpacket is asserted).
tx_etstamp_ins_ctrl_checksum_zero In 1 Assert this signal to set the checksum field of UDP/IPv4 to zero. Required offset location of checksum field. Assert this signal in the same clock cycle as the start of packet (avalon_st_tx_startofpacket is asserted).
tx_etstamp_ins_ctrl_checksum_correct In 1 Assert this signal to correct UDP/IPv6 packet checksum, by updating the checksum correction, which is specified by checksum correction offset. Required offset location of checksum correction. Assert this signal in the same clock cycle as the start of packet (avalon_st_tx_startofpacket is asserted).
tx_etstamp_ins_ctrl_offset_timestamp[15:0] In 16 The location of the timestamp field, relative to the first byte of the packet. Assert this signal in the same clock cycle as the start of packet (avalon_st_tx_startofpacket is asserted).
tx_etstamp_ins_ctrl_offset_correction_field[15:0] In 16 The location of the correction field, relative to the first byte of the packet. Assert this signal in the same clock cycle as the start of packet (avalon_st_tx_startofpacket is asserted).
tx_etstamp_ins_ctrl_offset_checksum_field[15:0] In 16 The location of the checksum field, relative to the first byte of the packet. Assert this signal in the same clock cycle as the start of packet (avalon_st_tx_startofpacket is asserted).
tx_etstamp_ins_ctrl_offset_checksum_correction[15:0] In 16 The location of the checksum correction field, relative to the first byte of the packet. Assert this signal in the same clock cycle as the start of packet (avalon_st_tx_startofpacket is asserted).
tx_egress_asymmetry_update In 1

Assert this signal to update the CF in the PTP header of transmit frame with asymmetry value. Assert this signal in the same clock cycle as the start of packet (avalon_st_tx_startofpacket) is asserted.

For more details, refer to related links about the tx_asymmetry register.

tx_time_of_day_96b_10g_data[95:0]

tx_time_of_day_96b_1g_data[95:0]

In 96 Carries the time-of-day (TOD) from an external TOD module to the MAC IP core in the following format:
  • Bits 48 to 95: 48-bit seconds field
  • Bits 16 to 47: 32-bit nanoseconds field
  • Bits 0 to 15: 16-bit fractional nanoseconds field

tx_time_of_day_64b_10g_data[63:0]

tx_time_of_day_64b_1g_data[63:0]

In 64 Carries the TOD from an external TOD module to the MAC IP core in the following format:
  • Bits 16 to 63: 48-bit nanoseconds field
  • Bits 0 to 15: 16-bit fractional nanoseconds field

tx_path_delay_10g_data[15:0]

In 16 Connect this bus to the PHY Intel® FPGA IP. This bus carries the path delay, which is measured between the physical network and the PHY side of the MAC IP Core (XGMII, GMII, or MII). The MAC IP core uses this value when generating the egress timestamp to account for the delay. The path delay is in the following format:
  • Bits 0 to 9: Fractional number of clock cycle
  • Bits 10 to 16/23: Number of clock cycle

tx_path_delay_10g_data[23:0] (for USXGMII speed mode)

In 24

tx_path_delay_1g_data[21:0]

In 22 Connect this bus to the PHY Intel® FPGA IP. This bus carries the path delay, which is measured between the physical network and the PHY side of the MAC IP Core (XGMII, GMII, or MII). The MAC IP core uses this value when generating the egress timestamp to account for the delay. The path delay is in the following format:
  • Bits 0 to 9: Fractional number of clock cycle
  • Bits 10 to 21: Number of clock cycle
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