Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

ID 813663
Date 7/08/2024
Public
Document Table of Contents

1. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview

Updated for:
Intel® Quartus® Prime Design Suite 24.2
IP Version 2.1.0

The Low Latency Ethernet 10G MAC Intel® FPGA IP is a configurable component that implements the IEEE 802.3-2008 specification. To build a complete Ethernet subsystem in an Intel FPGA device and connect it to an external device, you can use the Low Latency Ethernet 10G MAC Intel® FPGA IP with an Intel FPGA PHY IP or any of the supported PHYs.

The figure below shows a system with the Low Latency Ethernet 10G MAC Intel® FPGA IP.

Figure 1. Typical Application of Low Latency (LL) Ethernet 10G (10GbE) MAC

Note: Intel FPGAs implement and support the Low Latency Ethernet 10G MAC and 1G/2.5G/5G/10G Multirate Ethernet PHY (PCS + PMA) Intel® FPGA IPs to interface in a chip-to-chip or chip-to-module channel with external MGBASE (1G/2.5G) and NBASE (1G/2.5G/5G/10Gb Ethernet) PHY standard devices.
Note: Device support for Agilex™ 5 D-Series FPGAs and SoCs in the Quartus® Prime Pro Edition software version 24.2 is restricted. To enable D-Series device support in your instance of the Quartus® Prime Pro Edition software, contact your regional Altera sales representative.