Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

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ID 813266
Date 7/08/2024
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Document Table of Contents
Document Table of Contents x
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs x
1.1. Pins Status for Agilex™ 5 Devices 1.2. Agilex™ 5 FPGA Core Pins 1.3. Agilex™ 5 GTS Transceiver Pins 1.4. Agilex™ 5 Hard Processor System (HPS) Pins 1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices 1.6. Notes to Agilex™ 5 Pin Connection Guidelines 1.7. Document Revision History for the Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1.2. Agilex™ 5 FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. HVIO GPIO Pins 1.2.10. HVIO Optional Function Pins 1.2.11. No Connect and DNU Pins 1.2.12. Power Supply Pins 1.2.13. Secure Device Manager (SDM) Pins 1.2.14. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 5 GTS Transceiver Pins x
1.3.1. GTS Transceiver Power Supply Pins 1.3.2. GTS Transceiver Pins
1.4. Agilex™ 5 Hard Processor System (HPS) Pins x
1.4.1. HPS Power Supply Pins 1.4.2. HPS Oscillator Clock Input Pin 1.4.3. HPS JTAG Pins 1.4.4. HPS GPIO Pins 1.4.5. HPS SDMMC Pins 1.4.6. HPS NAND Pins 1.4.7. HPS USB Pins 1.4.8. HPS EMAC Pins 1.4.9. HPS I2C_EMAC and MDIO Pins 1.4.10. HPS I2C Pins 1.4.11. HPS I3C Pins 1.4.12. HPS SPI Pins 1.4.13. HPS UART Pins 1.4.14. HPS Trace Pins
1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices x
1.5.1. Example 1— Agilex™ 5 Devices with Speed Grade -1V, -2V, -2E, and -3V 1.5.2. Example 2— Agilex™ 5 Devices with Speed Grade -4S, -5S, -6S, and -6X
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

1.2.6. Voltage Sensor and Voltage Reference Pins

Note: Altera recommends that you create an Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software will check your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 7.  Voltage Sensor and Voltage Reference Pins
Pin Name Pin Functions Pin Description Connection Guidelines
VREFP_ADC Input Dedicated precision analog voltage reference.

Tie the VREFP_ADC pin to an external 1.25 V accurate reference source (± 0.1%) for better ADC performance.

Treat the VREFP_ADC as an analog signal together with the VREFN_ADC signal that provides a differential 1.25 V voltage.

If no external reference is supplied, always connect the VREFP_ADC pin to GND. An on-chip reference source (± 2%) is activated if the external voltage reference source is disabled.

VREFP_ADC must be equal to or lower than VCCA_PLL to prevent damage

VREFN_ADC Input

Tie the VREFN_ADC pin to the GND for better ADC performance.

Treat VREFN_ADC as an analog signal together with the VREFP_ADC signal that provides a differential 1.25 V voltage.

If no external reference is supplied, always connect the VREFN_ADC pin to GND.

VSIGP_[0,1] Input Analog differential inputs pins used with the voltage sensor inside the FPGA to monitor external analog voltages.

Tie these pins to GND if you do not use the voltage sensor feature. For more information on the usage of these pins, refer to the Power Management User Guide: Agilex™ 5 FPGAs and SoCs .

Do not drive the VSIGP and VSIGN pins until the VCCADC power rail has reached 1.62 V to prevent damage.

VSIGN_[0,1] Input
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