Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

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ID 813266
Date 11/21/2024
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Document Table of Contents
Document Table of Contents x
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs x
1.1. Pins Status for Agilex™ 5 Devices 1.2. Agilex™ 5 FPGA Core Pins 1.3. Agilex™ 5 GTS Transceiver Pins 1.4. Agilex™ 5 Hard Processor System (HPS) Pins 1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices 1.6. Notes to Agilex™ 5 Pin Connection Guidelines 1.7. Document Revision History for the Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1.2. Agilex™ 5 FPGA Core Pins x
1.2.1. Clock and PLL Pins 1.2.2. Dedicated Configuration/JTAG Pins 1.2.3. Optional/Dual-Purpose Configuration Pins 1.2.4. Differential I/O Pins 1.2.5. External Memory Interface Pins 1.2.6. Voltage Sensor and Voltage Reference Pins 1.2.7. Remote Temperature Sensing Diode Pins 1.2.8. Reference Pins 1.2.9. HVIO GPIO Pins 1.2.10. HVIO Optional Function Pins 1.2.11. No Connect and DNU Pins 1.2.12. Power Supply Pins 1.2.13. Secure Device Manager (SDM) Pins 1.2.14. Secure Device Manager (SDM) Optional Signal Pins
1.3. Agilex™ 5 GTS Transceiver Pins x
1.3.1. GTS Transceiver Power Supply Pins 1.3.2. GTS Transceiver Pins
1.4. Agilex™ 5 Hard Processor System (HPS) Pins x
1.4.1. HPS Power Supply Pins 1.4.2. HPS Oscillator Clock Input Pin 1.4.3. HPS JTAG Pins 1.4.4. HPS GPIO Pins 1.4.5. HPS SDMMC Pins 1.4.6. HPS NAND Pins 1.4.7. HPS USB Pins 1.4.8. HPS EMAC Pins 1.4.9. HPS I2C_EMAC and MDIO Pins 1.4.10. HPS I2C Pins 1.4.11. HPS I3C Pins 1.4.12. HPS SPI Pins 1.4.13. HPS UART Pins 1.4.14. HPS Trace Pins
1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices x
1.5.1. Example 1— Agilex™ 5 Devices with Speed Grade -1V, -2V, -2E, and -3V 1.5.2. Example 2— Agilex™ 5 Devices with Speed Grade -4S, -5S, -6S, and -6X
1. Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

1.2.12. Power Supply Pins

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Note: Altera recommends you to generate a .pin file from the Quartus® Prime Fitter to verify power pin assignment. Altera also recommends using this .pin file to determine if it is safe to power down or ground certain power supplies for your specific design. This step informs you to make the appropriate design choices for unused power supplies for your design.
Table 13.  Power Supply Pins
Pin Name Pin Functions Pin Description Connection Guidelines
VCCP Power VCCP supplies power to the periphery.

VCC and VCCP must operate at the same voltage level, should share the same power plane on the board, and be sourced from the same regulator.

For details about the recommended operating conditions, refer to the Electrical Characteristics section in the Agilex™ 5 FPGAs and SoCs Device Data Sheet .

Use the Intel® FPGA Power and Thermal Calculator and the Quartus® Prime Power Analyzer to determine the current requirements for VCCP and other power supplies. Decoupling for these pins depends on the decoupling requirements of the specific board.

VCC Power VCC supplies power to the core.

VCC and VCCP must operate at the same voltage level, should share the same power plane on the board, and be sourced from the same regulator.

For details about the recommended operating conditions, refer to the Electrical Characteristics section in the Agilex™ 5 FPGAs and SoCs Device Data Sheet .

Use the Intel® FPGA Power and Thermal Calculator and the Quartus® Prime Power Analyzer to determine the current requirements for VCC and other power supplies. Decoupling for these pins depends on the decoupling requirements of the specific board.

VCCPT Power Power supply for the IOPLL, programmable power technology, and I/O pre-drivers.

Connect VCCPT to a 1.8-V low noise switching regulator. You have the option to source the following from the same regulator as VCCPT:

  • VCCIO_SDM, VCCIO_HPS, and VCCPT_HVIO
  • VCCPLL_SDM, VCCPLL_HPS, and VCCADC with proper isolation filtering

Voltage spike ringing may be observed on VCCPT during device power-down sequencing if VCC is powered down before VCCPT, with the magnitude of the voltage spike ringing higher than VCCPT. This is the expected behavior and causes neither any functional failure nor reliability concerns to the device.

For more details about the decoupling recommendations for this voltage rail, refer to the Power Distribution Network Design Guidelines: Agilex™ 5 FPGAs and SoCs .

For the power rail sharing, refer to the Power Supply Sharing Guidelines for Agilex™ 5 Devices.

VCCRCORE Power Power supply for programmable power technology.

Connect the VCCRCORE to 1.2-V power supply.

You have the option to source VCCRCORE from the same regulator as VCCIO_PIO when you are using 1.2 V for VCCIO_PIO.

VCCH_SDM Power Voltage rail sense.

You must connect this sense to the VCCERT_GTS (1.0 V) rail for the Agilex™ 5 device with transceiver and connect this sense to VCCL_SDM for the device without transceiver.

VCCIO_PIO_2[A,B]T

VCCIO_PIO_2[A,B]B

VCCIO_PIO_3[A,B]T

VCCIO_PIO_3[A,B]B

Power

These are the supply voltage pins for the HSIO banks. Each sub-bank can support a different voltage level.

Supported VCCIO standards include the following:
  • 1.0-V
  • 1.05-V
  • 1.1-V
  • 1.2-V
  • 1.3-V

For more information about the supported pins, refer to the device pin-out file.

Connect these pins to a 1.0 V, 1.05 V, 1.1 V, 1.2 V, or 1.3 V power supplies, depending on the I/O standard required by the specific sub-bank.

When the entire HSIO bank is unused, you may connect the VCCIO_PIO of the unused HSIO bank to GND, 1.0 V, 1.05 V, 1.1 V, 1.2 V, or 1.3 V.

If only one of the sub-bank within the same HSIO bank is unused, you must connect the VCCIO_PIO of the unused sub-bank to the same VCCIO_PIO voltage level as the other actively utilized sub-bank.

Do not leave the VCCIO_PIO floating.

For the voltage tolerance (±3% or ±5%) in different use cases, refer to Agilex™ 5 FPGAs and SoCs Device Data Sheet .

For production device, you have option to connect VCCIO_PIO_T and VCCIO_PIO_B in the same I/O bank with different voltage level, for example, VCCIO_PIO_2AT (1.2 V) and VCCIO_PIO_2AB (1.1 V). For ES device, you must connect VCCIO_PIO_T and VCCIO_PIO_B in the same I/O bank with the same voltage level, for example, VCCIO_PIO_2AT (1.2 V) and VCCIO_PIO_2AB (1.2 V).

If you have LVDS Tx signals on the sub-bank of your board, the VCCIO_PIO of this sub-bank must be connected to 1.3 V.

During the power-up sequence only, a transient current whose magnitude is less than the VCCIO_PIO operating static current may be observed as the VCCIO_PIO transistors become operational. This is the expected behavior and causes neither any functional failure nor reliability concerns to the device if the power-up or power-down sequence is followed.

For more details, refer to the Power Management User Guide: Agilex™ 5 FPGAs and SoCs and General-Purpose I/O User Guide: Agilex™ 5 FPGAs and SoCs .

For the power rail sharing, refer to the Notes to the Agilex™ 5 Device Family Connection Guidelines section.

VCCIO_PIO_SDM Power VCCIO_PIO voltage rail sense line. Connect these pins to VCCIO_PIO_3AT as 1.2 V when you use Avalon® streaming interface x16 for FPGA configuration. Connect these pins to VCCRCORE if you do not use Avalon® streaming interface x16 for FPGA configuration.
VCCIO_SDM Power Configuration pins power supply.

Connect these pins to a 1.8-V power supply.

For more details about the decoupling recommendations for this voltage rail, refer to the Power Distribution Network Design Guidelines: Agilex™ 5 FPGAs and SoCs .

For the power rail sharing, refer to the Power Supply Sharing Guidelines for Agilex™ 5 Devices section.

VCCPLLDIG_SDM Power SDM block PLL power pins. VCCPLLDIG_SDM must be sourced from the same regulator as VCCL_SDM with proper isolation filtering.
VCCL_SDM Power SDM power supply. For the devices with speed grade -1V, -2V, -2E, -3V, and -4S, connect these pins to a 0.8-V power supply. For the devices with speed grade -5S, connect these pins to a 0.78-V power supply. For the devices with speed grade -6S and -6X, connect these pins to 0.75-V power supply.
VCCBAT Power Battery back-up power supply for device security Advanced Encryption Standard, Battery-backed RAM (AES BBRAM) key register.

When using the device security AES BBRAM key, connect this pin to a non-volatile battery power source in the range of 1.0 V to 1.8 V. A series RC (R=10 kΩ, C=1 µF) circuit must be added to the VCCBAT rail. Connect a 10-kΩ resistor in series between the battery power source and VCCBAT. The 1-uF capacitor is connected between VCCPT and GND.

For more information about the schematic diagram, refer to Power Distribution Network Design Guidelines: Agilex™ 5 FPGAs and SoCs .

Provide a minimum decoupling of 47 nF for the VCCBAT power rail near the VCCBAT pin.

When not using the AES BBRAM key, tie this pin to ground.
VCCPLL_SDM Power VCCPLL_SDM supplies analog power to the SDM block PLLs.

With proper isolation filtering, you have the option to source VCCPLL_SDM from the same regulator as VCCPT.

Decoupling for these pins depends on the design decoupling requirements of the specific board.

GND Ground Device ground pins. Connect all GND pins to the board ground plane.
VCCLSENSE Output Differential sense line to external regulator.

VCCLSENSE and GNDSENSE are differential remote sense pins for the VCC power. Connect the differential remote sense lines of your regulators to the respective VCCLSENSE and GNDSENSE pins. This compensates for the DC IR drop associated with the PCB and device package from the VCC power. Route these connections as differential pair traces and keep them isolated from any other noise source.

You must connect the VCCLSENSE and GNDSENSE lines to the regulator’s remote sense inputs. These two pins are only in the device which power speed grade is -V and -E.

GNDSENSE
VCCADC Power ADC power pin for the voltage sensors.

You must supply a low noise 1.8-V power supply to this pin if you are using the internal voltage sensors of the Agilex™ 5 device.

Tie this pin to VCCPT with proper isolation filtering.

VCCFUSEWR_SDM Power The required power supply to program (write) the optional, one-time programmable eFuses. These eFuses are an integral part of the Agilex™ 5 security architecture.

Connect this pin to 1.8-V. You must source VCCFUSEWR_SDM and VCCPT from the same 1.8-V regulator.

VCCPT_HVIO Power Pre-driver analog power supply pin for HVIO.

Connect these pins to a 1.8-V power supply. You must share the same regulator with VCCPT.

VCCIO_HVIO Power Buffer analog power supply pin for HVIO.

You can connect these pins to a 1.8-V, 2.5-V, or 3.3-V power supply.
VCCL_ADC_SDM Power HPS DSU and periphery voltage sense.

For the range of the VCCL_ADC_SDM power supply voltage, refer to the Agilex™ 5 FPGAs and SoCs Device Data Sheet .

VCCL_ADC_SDM can be shared with VCC.

Do not leave the VCCL_ADC_SDM floating or connected to GND.

VCC_IO_SDM Power SDM block I/O digital supply voltage sense.

For the range of the VCC_IO_SDM power supply voltage, refer to the Agilex™ 5 FPGAs and SoCs Device Data Sheet .

VCC_IO_SDM can be shared with VCC.

Do not leave the VCC_IO_SDM floating or connected to GND.

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