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1.1. Pins Status for Agilex™ 5 Devices
1.2. Agilex™ 5 FPGA Core Pins
1.3. Agilex™ 5 GTS Transceiver Pins
1.4. Agilex™ 5 Hard Processor System (HPS) Pins
1.5. Power Supply Sharing Guidelines for Agilex™ 5 Devices
1.6. Notes to Agilex™ 5 Pin Connection Guidelines
1.7. Document Revision History for the Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs
1.2.1. Clock and PLL Pins
1.2.2. Dedicated Configuration/JTAG Pins
1.2.3. Optional/Dual-Purpose Configuration Pins
1.2.4. Differential I/O Pins
1.2.5. External Memory Interface Pins
1.2.6. Voltage Sensor and Voltage Reference Pins
1.2.7. Remote Temperature Sensing Diode Pins
1.2.8. Reference Pins
1.2.9. HVIO GPIO Pins
1.2.10. HVIO Optional Function Pins
1.2.11. No Connect and DNU Pins
1.2.12. Power Supply Pins
1.2.13. Secure Device Manager (SDM) Pins
1.2.14. Secure Device Manager (SDM) Optional Signal Pins
1.4.1. HPS Power Supply Pins
1.4.2. HPS Oscillator Clock Input Pin
1.4.3. HPS JTAG Pins
1.4.4. HPS GPIO Pins
1.4.5. HPS SDMMC Pins
1.4.6. HPS NAND Pins
1.4.7. HPS USB Pins
1.4.8. HPS EMAC Pins
1.4.9. HPS I2C_EMAC and MDIO Pins
1.4.10. HPS I2C Pins
1.4.11. HPS I3C Pins
1.4.12. HPS SPI Pins
1.4.13. HPS UART Pins
1.4.14. HPS Trace Pins
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1.4.5. HPS SDMMC Pins
Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
HPS Pin Function | Pin Description and Connection Guidelines | Pin Type | Valid Assignments (select from one of the groups) | |
---|---|---|---|---|
Group 1 | Group 2 | |||
SDMMC_CLK | SDMMC clock out. | Output | HPS_IOA_3 | HPS_IOB_3 |
SDMMC_CMD | SDMMC command line. Pull this pin high on the board with a weak pull-up resistor. For example, a 10-kΩ to VCCIO_HPS. |
I/O | HPS_IOA_8 | HPS_IOB_8 |
SDMMC_DATA0 | SDMMC Data 0. | I/O | HPS_IOA_1 | HPS_IOB_1 |
SDMMC_DATA1 | SDMMC Data 1. | I/O | HPS_IOA_2 | HPS_IOB_2 |
SDMMC_DATA2 | SDMMC Data 2. | I/O | HPS_IOA_6 | HPS_IOB_6 |
SDMMC_DATA3 | SDMMC Data 3. When using SD card, there is an existing 50-kΩ pull-up on SDMMC Data Bit 3 which can be disabled in the HPS software by using the SET_CLR_CARD_DETECT (ACMD42) command. This is not applicable to the eMMC flash. |
I/O | HPS_IOA_7 | HPS_IOB_7 |
SDMMC_DATA4 | SDMMC Data 4. | I/O | HPS_IOA_9 | HPS_IOB_9 |
SDMMC_DATA5 | SDMMC Data 5. | I/O | HPS_IOA_10 | HPS_IOB_10 |
SDMMC_DATA6 | SDMMC Data 6. | I/O | HPS_IOA_11 | HPS_IOB_11 |
SDMMC_DATA7 | SDMMC Data 7. | I/O | HPS_IOA_12 | HPS_IOB_12 |
SDMMC_PWR_ENA | SDMMC Power Enable. Device bus power. Control switch to turn power on or off to the card. Optional. | Output | HPS_IOA_14 | HPS_IOB_14 |
SDMMC_WRITE_PROTECT | SDMMC Write Protect. | Input | HPS_IOA_5 | HPS_IOB_5 |
SDMMC_DATA_STROBE | SDMMC Data Strobe. | Input | HPS_IOA_16 | HPS_IOB_16 |
SDMMC_PU_PD_DATA2 | SDMMC pull-up/pull-down for pin DATA2. Used for 1.8 V operation without a level shifter, and LVSI compatible cards. | Output | HPS_IOA_13 | HPS_IOB_13 |