Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

ID 813266
Date 10/17/2024
Public
Document Table of Contents

1.4.2. HPS Oscillator Clock Input Pin

Note: Altera recommends that you create a Quartus® Prime design, enter your device I/O assignments, and compile the design. The Quartus® Prime software checks your pin connections according to I/O assignment and placement rules. The rules differ from one device to another based on device density, package, I/O assignments, voltage assignments, and other factors that are not fully described in this document or the device user guides.
Table 19.  HPS Oscillator Clock Input PinYou must provide one input clock source to the HPS.
HPS Pin Function Pin Description and Connection Guidelines Pin Type Valid Assignments
HPS_OSC_CLK

Clock input pin that drives the main PLL.

Connect a single-ended clock source to this pin. The I/O standard of the clock source must be compatible with VCCIO_HPS.

If you do not intend to utilize the HPS, you cannot use the HPS_OSC_CLK.

Input Select one of the 48 HPS dedicated I/O. For details of the supported frequency, refer to the Agilex™ 5 FPGAs and SoCs Device Data Sheet .