Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

ID 813266
Date 10/17/2024
Public
Document Table of Contents

1.7. Document Revision History for the Pin Connection Guidelines: Agilex™ 5 FPGAs and SoCs

Document Version Changes
2024.10.17
  • Updated Table: Differential I/O Pins:
    • Updated pin name DIFF_IO_[2][A,B][T,B][1:24][p,n] to DIFF_IO_[2][A,B]_[T,B][1:24][p,n].
    • Updated pin name DIFF_IO_[3][A,B][T,B][1:24][p,n] to DIFF_IO_[3][A,B]_[T,B][1:24][p,n].
  • Updated the VCCIO_PIO connection guidelines for unused HSIO bank and sub-bank in Table: Power Supply Pins.
  • Added new HPS I3C pins in Table: HPS I3C:
    • I3C0_SDA_PULLUP_EN
    • I3C1_SDA_PULLUP_EN
  • Updated the connection guidelines for the AS_nCSO3 pin function of SDM_IO8.
  • Made editorial edits to the connection guidelines of TCK and OSC_CLK_1 in Table: Dedicated Configuration/JTAG Pins for clarity.
2024.07.08 Updated the pin description and connection guidelines for PIN_PERST_N_CVP_L1[A,B,C,D]_[0,1] and PIN_PERST_N_R4[A,B,C,D]_[0,1].
2024.06.12 Updated the connection guidelines for the HPS_COLD_nRESET pin.
2024.04.02 Updated the connection guidelines for the following pins:
  • HPS_COLD_nRESET
  • HPS_OSC_CLK
  • JTAG_TCK
  • JTAG_TMS
  • JTAG_TDO
  • JTAG_TDI
  • GPIO0_IO[0..23]
  • GPIO1_IO[0..23]
2024.04.01 Initial release.