Visible to Intel only — GUID: bne1705039320294
Ixiasoft
Visible to Intel only — GUID: bne1705039320294
Ixiasoft
1.2.1. Clock and PLL Pins
Pin Name | Pin Functions | Pin Description | Connection Guidelines |
---|---|---|---|
CLK_[T,B]_2[A,B]_[0:1][p,n] CLK_[T,B]_3[A,B]_[0:1][p,n] |
I/O, Clock Input | Dual-purpose I/O pins that can be used for data inputs or outputs. On-chip termination such as differential input termination (RD OCT), parallel termination (RT OCT), and series termination (RS OCT) are supported on these pins. For more information about the supported pins, refer to the device pin-out file. When you do not use these pins as dedicated clock pins, you can use them as regular I/O pins. Supported I/O standards:
These pins support the programmable pull-up resistor. For more information, refer to the Agilex™ 5 FPGAs and SoCs Device Data Sheet . |
Tie the unused pins to GND or leave it as floating. If the pins are not connected, use the Quartus® Prime software programmable options to internally bias these pins. These pins can be reserved as inputs tristate with weak internal pull-up resistor enabled. |
PLL_[2][A,B]_[T,B]_FB[0:1] PLL_[3][A,B]_[T,B]_FB[0:1] |
I/O, Clock Input | Dual-purpose I/O pins that can be used as single-ended inputs, single-ended outputs, or external feedback input pins. For more information about the supported pins, refer to the device pin-out file. Supported I/O standards:
These pins support the programmable pull-up resistor. For more information, refer to the Agilex™ 5 FPGAs and SoCs Device Data Sheet . |
Tie the unused pins to GND or leave it as floating. If the pins are not connected, use the Quartus® Prime software programmable options to internally bias these pins. These pins can be reserved as inputs tristate with weak internal pull-up resistor enabled. |
PLL_[2][A,B]_[T,B]_CLKOUT[0:1][p,n] PLL_[3][A,B]_[T,B]_CLKOUT[0:1][p,n] |
I/O, Clock Output | I/O pins that can be used as two single-ended clock output pins or one differential clock output pair. For more information about the supported pins, refer to the device pin-out file. Supported I/O standards:
These pins support the programmable pull-up resistor. For more information, refer to the Agilex™ 5 FPGAs and SoCs Device Data Sheet . |
Tie the unused pins to GND or leave it as floating. If the pins are not connected, use the Quartus® Prime software programmable options to internally bias these pins. These pins can be reserved as inputs tristate with weak internal pull-up resistor enabled. |